| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2025-12-29 | Shut up verilators timescale warnings | uvok | |
| 2025-12-28 | p2s: Add valid output signal | uvok | |
| 2025-12-27 | p2s: Always use correct shift width | uvok | |
| 2025-12-27 | p2s: rewrite logic | uvok | |
| split blocks. Better separate counting/sending logic. | |||
| 2025-12-27 | Re-iterate par2ser | uvok | |
| 2025-12-26 | p2s: Fix logic and reset initialization | uvok | |
| also, don't use blocking assignments | |||
| 2025-12-26 | p2s: Rename input, improve latency | uvok | |
| start clock out data right away. | |||
| 2025-12-26 | continue complaining | uvok | |
| 2025-12-26 | Complain about timing | uvok | |
| 2025-12-26 | Add quick-and-dirty serial/parallel converters | uvok | |
 |
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |
path: root/par_to_ser.v