| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 13 days | linting, use different naming | uvok | |
| use _tb.v instead of .tb.v, to stop verilator from shouting the module name doesn't match | |||
| 13 days | p2s2p: Fix testbench | uvok | |
| iverilog syntax error (needs space) timing use logic, | |||
 |
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |
path: root/par_to_ser_to_par.tb.v