| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 13 days | s2p: Fix testbench | uvok | |
| needed data valid signal | |||
| 14 days | Shut up verilators timescale warnings | uvok | |
| 2025-12-28 | tb: Add dumpfilename macro | uvok | |
| 2025-12-26 | Make sense to s2p test bench | uvok | |
| 2025-12-26 | Add quick-and-dirty serial/parallel converters | uvok | |
 |
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |
path: root/ser_to_par.tb.v