| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 13 days | linting, use different naming | uvok | |
| use _tb.v instead of .tb.v, to stop verilator from shouting the module name doesn't match | |||
| 13 days | tst_delay: Fix testbench name | uvok | |
| 14 days | Shut up verilators timescale warnings | uvok | |
| 2025-12-28 | tb: Add dumpfilename macro | uvok | |
| 2025-12-28 | Add edge test | uvok | |
 |
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |
path: root/tst_delay.tb.v