From 0339e032a10a28df81800fcb6df9e688ba0706cd Mon Sep 17 00:00:00 2001
From: uvok
Date: Fri, 16 Jan 2026 18:55:24 +0100
Subject: eater: Connect RAM

---
 eater_cpu/eater_computer.sv    | 28 +++++++++++++++++++---------
 eater_cpu/eater_computer_tb.sv |  2 ++
 2 files changed, 21 insertions(+), 9 deletions(-)

diff --git a/eater_cpu/eater_computer.sv b/eater_cpu/eater_computer.sv
index cb94b86..b9863e8 100644
--- a/eater_cpu/eater_computer.sv
+++ b/eater_cpu/eater_computer.sv
@@ -14,22 +14,32 @@ module eater_computer(
 `include "../playground/my_mem.v"
 `endif
 
-my_mem #(
-  .DATA_WIDTH(8),
-  .DATA_DEPTH(16)
-) RAM (
-
-);
-
-
 /* verilator public_on */
-tri [7:0] bus, A_out, B_out;
+tri [7:0] bus, A_out, B_out, RAM_out;
 logic A_to_bus, bus_to_A,
       B_to_bus, bus_to_B,
       INS_to_bus, bus_to_INS,
+      RAM_to_bus, bus_to_RAM,
       ALU_to_bus
 ;
 
+my_mem #(
+  .DATA_WIDTH(8),
+  .DATA_DEPTH(16)
+) RAM (
+  .clk_i(clk_in),
+  .write_en_i(bus_to_RAM),
+  // ???
+  .read_en_i(RAM_to_bus),
+  .r_read_addr(),
+  .r_write_addr(),
+  .data_i(bus),
+  .data_o(),
+  .async_data_o(RAM_out)
+);
+
+assign bus = RAM_to_bus ? RAM_out : 8'bz;
+
 assign debug_bus = bus;
 /* verilator public_off */
 
diff --git a/eater_cpu/eater_computer_tb.sv b/eater_cpu/eater_computer_tb.sv
index 5739dc0..d5459bc 100644
--- a/eater_cpu/eater_computer_tb.sv
+++ b/eater_cpu/eater_computer_tb.sv
@@ -28,9 +28,11 @@ initial begin
   uut.B_to_bus = 0;
   uut.INS_to_bus = 0;
   uut.ALU_to_bus = 0;
+  uut.RAM_to_bus = 0;
   uut.bus_to_A = 0;
   uut.bus_to_B = 0;
   uut.bus_to_INS = 0;
+  uut.bus_to_RAM = 0;
   clk_in = 0;
   debug_enable = 0;
   debug_value = 'z;
-- 
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