From 0f9b0dd686f816c9e18debbbe9523ac0de683acf Mon Sep 17 00:00:00 2001
From: uvok
Date: Thu, 1 Jan 2026 16:05:00 +0100
Subject: tbs: remove e empty parens

---
 debounce_tb.v          | 3 +--
 fifo_tb.v              | 3 +--
 fizzbuzz_tb.v          | 3 +--
 led_toggle_bouncy_tb.v | 3 +--
 led_toggle_tb.v        | 3 +--
 par_to_ser_tb.v        | 3 +--
 par_to_ser_to_par_tb.v | 3 +--
 ser_to_par_tb.v        | 3 +--
 template_tb.v          | 3 +--
 tst_delay_tb.v         | 3 +--
 10 files changed, 10 insertions(+), 20 deletions(-)

diff --git a/debounce_tb.v b/debounce_tb.v
index a7017c7..fb9430c 100644
--- a/debounce_tb.v
+++ b/debounce_tb.v
@@ -1,7 +1,6 @@
 `timescale 1us/1us
 
-module debounce_tb (
-);
+module debounce_tb;
 
 logic rst_i;
 logic clk_i;
diff --git a/fifo_tb.v b/fifo_tb.v
index 4b1423c..38199a6 100644
--- a/fifo_tb.v
+++ b/fifo_tb.v
@@ -1,7 +1,6 @@
 `timescale 1us/1us
 
-module fifo_tb (
-);
+module fifo_tb;
 
 reg clk_i;
 reg rst_i;
diff --git a/fizzbuzz_tb.v b/fizzbuzz_tb.v
index 2a8cdff..4d612ec 100644
--- a/fizzbuzz_tb.v
+++ b/fizzbuzz_tb.v
@@ -1,7 +1,6 @@
 `timescale 1us/1us
 
-module fizzbuzz_tb (
-);
+module fizzbuzz_tb;
 
 
 logic [7:0] number;
diff --git a/led_toggle_bouncy_tb.v b/led_toggle_bouncy_tb.v
index f300071..2c04484 100644
--- a/led_toggle_bouncy_tb.v
+++ b/led_toggle_bouncy_tb.v
@@ -1,7 +1,6 @@
 `timescale 1us/1us
 
-module led_toggle_bouncy_tb (
-);
+module led_toggle_bouncy_tb;
 
 logic clk_i;
 logic key_i;
diff --git a/led_toggle_tb.v b/led_toggle_tb.v
index f5f4fd5..78d4f21 100644
--- a/led_toggle_tb.v
+++ b/led_toggle_tb.v
@@ -1,7 +1,6 @@
 `timescale 1us/1us
 
-module led_toggle_tb (
-);
+module led_toggle_tb;
 
 logic clk_i;
 logic rst_i;
diff --git a/par_to_ser_tb.v b/par_to_ser_tb.v
index edb1f9b..a30e282 100644
--- a/par_to_ser_tb.v
+++ b/par_to_ser_tb.v
@@ -1,7 +1,6 @@
 `timescale 1us/1us
 
-module par_to_ser_tb (
-);
+module par_to_ser_tb;
 
 logic clk_i;
 logic rst_i;
diff --git a/par_to_ser_to_par_tb.v b/par_to_ser_to_par_tb.v
index c422d86..9a4a3eb 100644
--- a/par_to_ser_to_par_tb.v
+++ b/par_to_ser_to_par_tb.v
@@ -3,8 +3,7 @@
 
 `timescale 1us/1us
 
-module par_to_ser_to_par_tb (
-);
+module par_to_ser_to_par_tb;
 
 logic clk_i;
 logic rst_i;
diff --git a/ser_to_par_tb.v b/ser_to_par_tb.v
index e82b56e..d39598e 100644
--- a/ser_to_par_tb.v
+++ b/ser_to_par_tb.v
@@ -1,7 +1,6 @@
 `timescale 1us/1us
 
-module ser_to_par_tb (
-);
+module ser_to_par_tb;
 
 logic clk_i;
 logic rst_i;
diff --git a/template_tb.v b/template_tb.v
index 3526168..8bef3a1 100644
--- a/template_tb.v
+++ b/template_tb.v
@@ -1,7 +1,6 @@
 `timescale 1us/1us
 
-module template_tb (
-);
+module template_tb;
 
 reg clk_i;
 reg rst_i;
diff --git a/tst_delay_tb.v b/tst_delay_tb.v
index 03ef185..5812068 100644
--- a/tst_delay_tb.v
+++ b/tst_delay_tb.v
@@ -1,8 +1,7 @@
 // try to figure out how iverilog samples edges
 `timescale 1us/1us
 
-module tst_delay_tb (
-);
+module tst_delay_tb;
 
 reg clk_i;
 reg data_i;
-- 
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