From 23e86f28d75f9de1f7f4658e99f2ae4eba48b48f Mon Sep 17 00:00:00 2001
From: uvok
Date: Sun, 28 Dec 2025 12:51:46 +0100
Subject: Add edge test

---
 tst_delay.tb.v | 44 ++++++++++++++++++++++++++++++++++++++++++++
 tst_delay.v    | 15 +++++++++++++++
 2 files changed, 59 insertions(+)
 create mode 100644 tst_delay.tb.v
 create mode 100644 tst_delay.v

diff --git a/tst_delay.tb.v b/tst_delay.tb.v
new file mode 100644
index 0000000..e82c541
--- /dev/null
+++ b/tst_delay.tb.v
@@ -0,0 +1,44 @@
+// try to figure out how iverilog samples edges
+`timescale 1us/1ns
+
+module template_tb (
+);
+
+reg clk_i;
+reg data_i;
+wire data_o;
+
+tst_delay uut(
+  .clk_i(clk_i),
+  .data_i(data_i),
+  .data_o(data_o)
+);
+
+initial begin
+  $dumpfile("tst_delay.lxt2"); $dumpvars();
+  clk_i = 0;
+  data_i = 0;
+end
+
+always #10 clk_i = ~clk_i;
+
+initial begin
+  #9
+  data_i = 1;
+  #2
+  data_i = 0;
+  // note the <= assignment
+  #19
+  data_i <= 1;
+  #1
+  data_i = 0;
+  // note the = assignment
+  #19
+  data_i = 1;
+  #1
+  data_i = 0;
+  #40
+  $finish();
+end
+
+endmodule
diff --git a/tst_delay.v b/tst_delay.v
new file mode 100644
index 0000000..fbc7c85
--- /dev/null
+++ b/tst_delay.v
@@ -0,0 +1,15 @@
+module tst_delay (
+  input clk_i,
+  input data_i,
+  output reg data_o
+);
+
+initial begin
+  data_o = 0;
+end
+
+always @(posedge clk_i) begin
+  data_o <= data_i;
+end
+
+endmodule
-- 
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