From 282c232e01a2bfd42b07a78bec7c366b9caec16d Mon Sep 17 00:00:00 2001
From: uvok
Date: Sat, 27 Dec 2025 11:57:07 +0100
Subject: p2s: Always use correct shift width

---
 par_to_ser.v | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/par_to_ser.v b/par_to_ser.v
index d4e4254..8c814c4 100644
--- a/par_to_ser.v
+++ b/par_to_ser.v
@@ -1,7 +1,7 @@
 // parallel to serial converter
 
 module par_to_ser #(
-  SHIFT_WIDTH = 8
+  parameter SHIFT_WIDTH = 8
 ) (
   input rst_i,
   input clk_i,
@@ -14,16 +14,14 @@ module par_to_ser #(
 // if I want to use it in the input/output list.
 // parameter SHIFT_WIDTH = 8;
 
-reg [7:0] send_data = 8'hff;
+reg [(SHIFT_WIDTH-1):0] send_data = {SHIFT_WIDTH{1'b1}};
 // want to count to number *including* width, add 1
 reg [$clog2(SHIFT_WIDTH + 1) - 1:0] count = 0;
 
-wire counting, sending;
-
-// sending is one byte longer
-assign sending = (count != 0) && (count <= SHIFT_WIDTH);
 // yes, smaller than, the count *to* 8 still takes place
-assign counting = (count != 0) && (count < SHIFT_WIDTH);
+wire counting = (count != 0) && (count < SHIFT_WIDTH);
+// sending is one byte longer
+wire sending = (count != 0) && (count <= SHIFT_WIDTH);
 
 always @(posedge clk_i or negedge rst_i) begin
   if (!rst_i) begin
@@ -37,12 +35,12 @@ end
 
 always @(posedge clk_i or negedge rst_i) begin
   if (!rst_i) begin
-    send_data <= 8'hff;
+    send_data <= {SHIFT_WIDTH{1'b1}};
   end else if (data_valid_i && count == 0) begin
-    send_data <= {1'b1, dat_i[7:1]};
+    send_data <= {1'b1, dat_i[(SHIFT_WIDTH-1):1]};
   end else if (sending) begin
     // arbitrary decision: register is filled with a 1
-    send_data <= {1'b1, send_data[7:1]};
+    send_data <= {1'b1, send_data[(SHIFT_WIDTH-1):1]};
   end
 end
 
-- 
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