From 3cb63dec5174fa442463ad150a6f3c4aa61a4cef Mon Sep 17 00:00:00 2001
From: uvok
Date: Fri, 16 Jan 2026 17:46:14 +0100
Subject: Add link to (S)Verilog datatype

---
 README.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/README.txt b/README.txt
index f040223..5ff79e7 100644
--- a/README.txt
+++ b/README.txt
@@ -36,3 +36,7 @@ Questions:
     It "somehow just works".
     Or rather, stuff is delayed by one clock cycle, e.g.
     when chaining flip-flops together.
+
+# Random links
+
+https://chipmunklogic.com/digital-logic-design/logic-vs-wire-in-system-verilog-some-misconceptions/
-- 
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