From 539e67d451e267fb8c6040bc95c64894372e8b66 Mon Sep 17 00:00:00 2001
From: uvok
Date: Fri, 26 Dec 2025 15:15:52 +0100
Subject: Add comment/docu

---
 debounce.v | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/debounce.v b/debounce.v
index 014f7c4..9f0a0e2 100644
--- a/debounce.v
+++ b/debounce.v
@@ -16,6 +16,10 @@ reg prev_state;
 
 always @(posedge clk_i or negedge rst_i) begin
   if (!rst_i) begin
+    // Learning: I would like to set the output to the input on reset
+    // but then I get
+    // Warning: Async reset value `\signal_i' is not constant!
+    // and a synthesis error.
     clk_counter <= 0;
     prev_state <= INIT_SIG_STATE;
     signal_o <= INIT_SIG_STATE;
-- 
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