From 6db8308fd1897a38a4fc489437973ac8c8cee0ea Mon Sep 17 00:00:00 2001
From: uvok
Date: Sun, 28 Dec 2025 15:24:54 +0100
Subject: add fifo

---
 fifo.tb.v | 34 ++++++++++++++++++++++++++++++++++
 fifo.v    | 27 +++++++++++++++++++++++++++
 2 files changed, 61 insertions(+)
 create mode 100644 fifo.tb.v
 create mode 100644 fifo.v

diff --git a/fifo.tb.v b/fifo.tb.v
new file mode 100644
index 0000000..b948cf1
--- /dev/null
+++ b/fifo.tb.v
@@ -0,0 +1,34 @@
+`timescale 1us/1ns
+
+module fifo_tb (
+);
+
+reg clk_i;
+reg rst_i;
+
+fifo uut(
+  .clk_i(clk_i),
+  .rst_i(rst_i)
+);
+
+string filename;
+initial begin
+`ifdef DUMP_FILE_NAME
+  filename=`DUMP_FILE_NAME;
+`else
+  filename="fifo.lxt2";
+`endif
+  $dumpfile(filename); $dumpvars();
+  clk_i <= 0;
+  rst_i <= 1'b1;
+
+end
+
+always #10 clk_i = ~clk_i;
+
+initial begin
+  #100
+  $finish();
+end
+
+endmodule
diff --git a/fifo.v b/fifo.v
new file mode 100644
index 0000000..d900155
--- /dev/null
+++ b/fifo.v
@@ -0,0 +1,27 @@
+module fifo #(
+  parameter DATA_WIDTH = 8,
+  parameter DATA_DEPTH = 1024
+) (
+  input rst_i,
+  input clk_i,
+
+  input data_write_i,
+  input data_read_i,
+
+  output empty_o,
+  output full_o,
+
+  output data_valid_o,
+
+  input [(DATA_WIDTH-1) : 0] data_i,
+  output [(DATA_WIDTH-1) : 0] data_o
+
+);
+
+always @(posedge clk_i or negedge rst_i) begin
+  if (!rst_i) begin
+    
+  end
+end
+
+endmodule
-- 
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