From 853bc8e1b782af25e95bf3582cf5069eec6e67d4 Mon Sep 17 00:00:00 2001
From: uvok
Date: Fri, 26 Dec 2025 18:08:19 +0100
Subject: Complain about timing

---
 par_to_ser.v | 6 ++++++
 ser_to_par.v | 5 +++++
 2 files changed, 11 insertions(+)

diff --git a/par_to_ser.v b/par_to_ser.v
index a71abec..5e261a9 100644
--- a/par_to_ser.v
+++ b/par_to_ser.v
@@ -15,6 +15,12 @@ module par_to_ser (
 reg sending = 1'b0;
 reg [7:0] send_data = 8'hff;
 
+// Learning:
+// Ugh, this is fucking stupid.
+// if I send out directly at the rising clock edge,
+// the output will violate setup and hold times???
+//
+
 always @(posedge clk_i or negedge rst_i) begin
   if (!rst_i) begin
     dat_o <= 1'b1;
diff --git a/ser_to_par.v b/ser_to_par.v
index 754fdc0..d56dd03 100644
--- a/ser_to_par.v
+++ b/ser_to_par.v
@@ -11,6 +11,11 @@ module ser_to_par (
   output reg[7:0] dat_o
 );
 
+// Learning:
+// Ugh, this is fucking stupid.
+// if I send out directly at the rising clock edge,
+// the output will violate setup and hold times???
+//
 always @(posedge clk_i or negedge rst_i) begin
   if (!rst_i) begin
     dat_o <= 8'b0;
-- 
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