From 89b32b416d23063f42bef5418aa825893bd33b4b Mon Sep 17 00:00:00 2001
From: uvok
Date: Wed, 24 Dec 2025 17:50:33 +0100
Subject: clkdiv: output must be a register

---
 clkdiv.v | 5 ++---
 led.v    | 4 ++--
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/clkdiv.v b/clkdiv.v
index aef93eb..7cf6cc3 100644
--- a/clkdiv.v
+++ b/clkdiv.v
@@ -1,7 +1,7 @@
 module clkdiv (
     input rst_i,
     input clk,              // clk input
-    output o_divclk
+    output reg o_divclk     // divided output (must be a reg, b/c it needs to keep state)
 );
 
 reg [23:0] counter;
@@ -19,9 +19,8 @@ end
 always @(posedge clk or negedge rst_i) begin
     if (!rst_i)
         o_divclk <= 1'b0;
-//    else if (counter == 24'd1349_9999)       // 0.5s delay
     else if (counter == 24'd674_9999)       // 0.5s delay
-        o_divclk[0] <= o_divclk[0] + 1;
+        o_divclk <= ~o_divclk;
     else
         o_divclk <= o_divclk;
 end
diff --git a/led.v b/led.v
index e99e5ba..2827b87 100644
--- a/led.v
+++ b/led.v
@@ -6,7 +6,7 @@ module led (
     output reg [5:0] led    // 6 LEDS pin
 );
 
-wire myclk;
+reg myclk;
 
 clkdiv bla(
   .rst_i(rst_i),
@@ -16,7 +16,7 @@ clkdiv bla(
 
 always @(posedge myclk or negedge rst_i) begin
     if (!rst_i)
-        led <= 6'b011110;
+        led <= 6'b111111;
     else
 //    else if (counter == 24'd1349_9999)       // 0.5s delay
         led[5:0] <= led[5:0] - 1;
-- 
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