From 9f59b209be81ab38976218a978738b83b4429b2c Mon Sep 17 00:00:00 2001
From: uvok
Date: Sun, 18 Jan 2026 16:31:38 +0100
Subject: eater: Add OUT reg

---
 eater_cpu/eater_computer.sv | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/eater_cpu/eater_computer.sv b/eater_cpu/eater_computer.sv
index 41d66b6..f71bde9 100644
--- a/eater_cpu/eater_computer.sv
+++ b/eater_cpu/eater_computer.sv
@@ -30,7 +30,9 @@ wire [7:0]
       // feeds into RAM, at least the LSB.
       MAR_out,
       // PC is only 4 bit, but to output to bus, we want to pad with 0es.
-      PC_out_full
+      PC_out_full,
+      // OUT->Display output
+      OUT_out
 ;
 
 // PC is only 4 bit.
@@ -43,7 +45,8 @@ logic
       RAM_to_bus, bus_to_RAM,
       ALU_to_bus,
       PC_to_bus, bus_to_PC, PC_count_en,
-      bus_to_MAR
+      bus_to_MAR,
+      bus_to_OUT
 ;
 
 /* verilator public_off */
@@ -153,4 +156,13 @@ zbuffer PC_to_bus_buffer (
     .data_out(bus)
 );
 
+eater_register OUT (
+  .clk_in(clk_in),
+  .data_in(bus),
+  .en_store_in(bus_to_OUT),
+  .en_output_in(1'b0),
+  .bus_out(),
+  .always_out(OUT_out)
+);
+
 endmodule
-- 
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