From cfd07649c45036241239668c0e0061e61a5f8440 Mon Sep 17 00:00:00 2001
From: uvok
Date: Thu, 25 Dec 2025 11:15:38 +0100
Subject: Remove explicit synth and deps rule

explicit rule prevents it from being an intermediate file
---
 Makefile | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/Makefile b/Makefile
index 9f38548..de8af58 100644
--- a/Makefile
+++ b/Makefile
@@ -26,7 +26,7 @@ tangnano9k.cst:
 	curl -LO https://github.com/YosysHQ/apicula/raw/refs/heads/master/examples/tangnano9k.cst
 
 ## helper targets
-.PHONY: clean flash show synth deps
+.PHONY: clean flash show
 show: $(PROGRAM).v
 	yosys -p "read_verilog $<; show $(PROGRAM)"
 
@@ -36,10 +36,6 @@ flash: $(PROGRAM).fs
 clean:
 	rm -rf *.json *.fs *.svg *.log *.dep
 
-synth: $(PROGRAM).json
-
-deps: $(PROGRAM).dep
-
 ## Patterns
 
 # synthesize
-- 
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