From d0a372c3112b28ff3b1bf03ff4a7a0e5a3cafe8e Mon Sep 17 00:00:00 2001
From: uvok
Date: Tue, 30 Dec 2025 10:21:27 +0100
Subject: linting, use different naming

use _tb.v instead of .tb.v,
to stop verilator from shouting
the module name doesn't
match
---
 Makefile               |  8 ++--
 debounce.tb.v          | 77 ---------------------------------------
 debounce_tb.v          | 77 +++++++++++++++++++++++++++++++++++++++
 fifo.tb.v              | 69 -----------------------------------
 fifo.v                 |  1 +
 fifo_tb.v              | 73 +++++++++++++++++++++++++++++++++++++
 fizzbuzz.tb.v          | 49 -------------------------
 fizzbuzz_tb.v          | 49 +++++++++++++++++++++++++
 led_toggle.tb.v        | 60 ------------------------------
 led_toggle_bouncy.tb.v | 51 --------------------------
 led_toggle_bouncy_tb.v | 51 ++++++++++++++++++++++++++
 led_toggle_tb.v        | 60 ++++++++++++++++++++++++++++++
 my_mem.tb.v            | 99 --------------------------------------------------
 my_mem_tb.v            | 99 ++++++++++++++++++++++++++++++++++++++++++++++++++
 par_to_ser.tb.v        | 69 -----------------------------------
 par_to_ser_tb.v        | 69 +++++++++++++++++++++++++++++++++++
 par_to_ser_to_par.tb.v | 82 -----------------------------------------
 par_to_ser_to_par_tb.v | 82 +++++++++++++++++++++++++++++++++++++++++
 ser_to_par.tb.v        | 63 --------------------------------
 ser_to_par_tb.v        | 63 ++++++++++++++++++++++++++++++++
 template.tb.v          | 37 -------------------
 template_tb.v          | 37 +++++++++++++++++++
 tst_delay.tb.v         | 50 -------------------------
 tst_delay_tb.v         | 54 +++++++++++++++++++++++++++
 24 files changed, 719 insertions(+), 710 deletions(-)
 delete mode 100644 debounce.tb.v
 create mode 100644 debounce_tb.v
 delete mode 100644 fifo.tb.v
 create mode 100644 fifo_tb.v
 delete mode 100644 fizzbuzz.tb.v
 create mode 100644 fizzbuzz_tb.v
 delete mode 100644 led_toggle.tb.v
 delete mode 100644 led_toggle_bouncy.tb.v
 create mode 100644 led_toggle_bouncy_tb.v
 create mode 100644 led_toggle_tb.v
 delete mode 100644 my_mem.tb.v
 create mode 100644 my_mem_tb.v
 delete mode 100644 par_to_ser.tb.v
 create mode 100644 par_to_ser_tb.v
 delete mode 100644 par_to_ser_to_par.tb.v
 create mode 100644 par_to_ser_to_par_tb.v
 delete mode 100644 ser_to_par.tb.v
 create mode 100644 ser_to_par_tb.v
 delete mode 100644 template.tb.v
 create mode 100644 template_tb.v
 delete mode 100644 tst_delay.tb.v
 create mode 100644 tst_delay_tb.v

diff --git a/Makefile b/Makefile
index 06a693a..94c301c 100644
--- a/Makefile
+++ b/Makefile
@@ -96,14 +96,14 @@ lint: $(PROGRAM).v
 %.lxt2: %.vvp
 	./$< -lxt2
 
-%.vvp: %.v %.tb.v
-	iverilog -DDUMP_FILE_NAME='"$*.lxt2"' -g2012 -o $*.vvp $*.v $*.tb.v
+%.vvp: %.v %_tb.v
+	iverilog -DDUMP_FILE_NAME='"$*.lxt2"' -g2012 -o $*.vvp $*.v $*_tb.v
 
 # verilog unfortunately exits on any warning
 # also on warnings "boohoo, you specified timings in some modules and not in others"
 # since this is fucking annoying, I choose to ignore the exit code.
-verilator.%: %.v %.tb.v
-	verilator --quiet -DDUMP_FILE_NAME='"dump.vvp"' --trace --timing --main --exe --Mdir verilator.$(PROGRAM) $(PROGRAM).tb.v || true
+verilator.%: %.v %_tb.v
+	verilator --quiet -DDUMP_FILE_NAME='"dump.vvp"' --trace --timing --main --exe --Mdir verilator.$(*) $(*)_tb.v || true
 
 # need to specify RM for some reason
 # verilators makefiles doesn't specify the variable
diff --git a/debounce.tb.v b/debounce.tb.v
deleted file mode 100644
index 3376434..0000000
--- a/debounce.tb.v
+++ /dev/null
@@ -1,77 +0,0 @@
-`timescale 1us/1us
-
-module debounce_tb (
-);
-
-logic rst_i;
-logic clk_i;
-logic signal_i;
-logic signal_o;
-
-integer i = 0;
-
-debounce #(.STABLE_PERIOD(5)) uut(
-  .rst_i(rst_i),
-  .clk_i(clk_i),
-  .signal_i(signal_i),
-  .signal_o(signal_o)
-);
-
-string filename;
-initial begin
-`ifdef DUMP_FILE_NAME
-  filename=`DUMP_FILE_NAME;
-`else
-  filename="debounce.lxt2";
-`endif
-  $dumpfile(filename); $dumpvars();
-
-  clk_i = 0;
-  rst_i = 1'b1;
-  signal_i = 1'b1;
-  #1
-  rst_i = 1'b0;
-  #1
-  rst_i = 1'b1;
-end
-
-always #10 clk_i = ~clk_i;
-
-initial begin
-  // initial key press
-  @(negedge clk_i);
-  signal_i = ~signal_i;
-  assert (signal_o == 1'b1);
- 
-  repeat(2) @(negedge clk_i);
- 
-  signal_i = ~signal_i;
-  assert (signal_o == 1'b1);
-
-  // try bouncing
-
-  repeat(2) @(negedge clk_i);
-
-  for (i=0; i < 20; i = i + 1) begin
-    @(negedge clk_i);
-    signal_i = ~signal_i;
-    assert (signal_o == 1'b1);
-  end
-  @(negedge clk_i);
-  signal_i = ~signal_i;
-  assert (signal_o == 1'b1);
-
-  repeat(10) @(negedge clk_i);
-  assert (signal_o == 1'b0);
-
-  repeat(10) @(negedge clk_i);
-  signal_i = ~signal_i;
-
-  repeat(10) @(negedge clk_i);
-  assert (signal_o == 1'b1);
-
-  repeat(10) @(negedge clk_i);
-  $finish();
-end
-
-endmodule
diff --git a/debounce_tb.v b/debounce_tb.v
new file mode 100644
index 0000000..a7017c7
--- /dev/null
+++ b/debounce_tb.v
@@ -0,0 +1,77 @@
+`timescale 1us/1us
+
+module debounce_tb (
+);
+
+logic rst_i;
+logic clk_i;
+logic signal_i;
+logic signal_o;
+
+integer i = 0;
+
+debounce #(.STABLE_PERIOD(5)) uut (
+  .rst_i(rst_i),
+  .clk_i(clk_i),
+  .signal_i(signal_i),
+  .signal_o(signal_o)
+);
+
+string filename;
+initial begin
+`ifdef DUMP_FILE_NAME
+  filename=`DUMP_FILE_NAME;
+`else
+  filename="debounce.lxt2";
+`endif
+  $dumpfile(filename); $dumpvars();
+
+  clk_i = 0;
+  rst_i = 1'b1;
+  signal_i = 1'b1;
+  #1
+  rst_i = 1'b0;
+  #1
+  rst_i = 1'b1;
+end
+
+always #10 clk_i = ~clk_i;
+
+initial begin
+  // initial key press
+  @(negedge clk_i);
+  signal_i = ~signal_i;
+  assert (signal_o == 1'b1);
+ 
+  repeat(2) @(negedge clk_i);
+ 
+  signal_i = ~signal_i;
+  assert (signal_o == 1'b1);
+
+  // try bouncing
+
+  repeat(2) @(negedge clk_i);
+
+  for (i=0; i < 20; i = i + 1) begin
+    @(negedge clk_i);
+    signal_i = ~signal_i;
+    assert (signal_o == 1'b1);
+  end
+  @(negedge clk_i);
+  signal_i = ~signal_i;
+  assert (signal_o == 1'b1);
+
+  repeat(10) @(negedge clk_i);
+  assert (signal_o == 1'b0);
+
+  repeat(10) @(negedge clk_i);
+  signal_i = ~signal_i;
+
+  repeat(10) @(negedge clk_i);
+  assert (signal_o == 1'b1);
+
+  repeat(10) @(negedge clk_i);
+  $finish();
+end
+
+endmodule
diff --git a/fifo.tb.v b/fifo.tb.v
deleted file mode 100644
index 3238eba..0000000
--- a/fifo.tb.v
+++ /dev/null
@@ -1,69 +0,0 @@
-`timescale 1us/1us
-
-module fifo_tb (
-);
-
-reg clk_i;
-reg rst_i;
-
-reg read_i, write_i;
-reg [7:0] data_i;
-
-fifo #(
-  .DATA_WIDTH(8),
-  .DATA_DEPTH(8)
-) uut(
-  .clk_i(clk_i),
-  .rst_i(rst_i),
-  .write_i(write_i),
-  .read_i(read_i),
-  .data_i
-);
-
-string filename;
-initial begin
-`ifdef DUMP_FILE_NAME
-  filename=`DUMP_FILE_NAME;
-`else
-  filename="fifo.lxt2";
-`endif
-  $dumpfile(filename); $dumpvars();
-  clk_i <= 0;
-  rst_i <= 1'b1;
-  read_i = 0;
-  write_i = 0;
-  data_i = 0;
-end
-
-always #10 clk_i = ~clk_i;
-
-initial begin
-  #15
-
-  for (integer run = 1; run < 3; run++) begin
-  
-    write_i = 1;
-    for (integer addr = 0; addr < 10; addr++) begin
-
-      data_i = (run << 4) | addr;
-      #20
-      ;
-    end
-
-    write_i = 0;
-    read_i = 1;
-
-    for (integer addr = 0; addr < 10; addr++) begin
-      #20
-      ;
-    end
-
-    read_i = 0;
-    #20
-    ;
-  end
-  #100
-  $finish();
-end
-
-endmodule
diff --git a/fifo.v b/fifo.v
index 30b963e..bcc2d3f 100644
--- a/fifo.v
+++ b/fifo.v
@@ -27,6 +27,7 @@ localparam DATA_DEPTH_BITS = $clog2(DATA_DEPTH);
 // the -1 will make sure it fits
 /* verilator lint_off WIDTHTRUNC */
 localparam [DATA_DEPTH_BITS-1:0] MAX_ADDRESS = (DATA_DEPTH - 1);
+/* verilator lint_on WIDTHTRUNC */
 
 // need to "count" to number *including* depth
 reg [$clog2(DATA_DEPTH + 1)-1:0] r_count;
diff --git a/fifo_tb.v b/fifo_tb.v
new file mode 100644
index 0000000..4b1423c
--- /dev/null
+++ b/fifo_tb.v
@@ -0,0 +1,73 @@
+`timescale 1us/1us
+
+module fifo_tb (
+);
+
+reg clk_i;
+reg rst_i;
+
+reg read_i, write_i;
+reg [7:0] data_i;
+
+fifo #(
+  .DATA_WIDTH(8),
+  .DATA_DEPTH(8)
+) uut (
+  .clk_i(clk_i),
+  .rst_i(rst_i),
+  .write_i(write_i),
+  .read_i(read_i),
+  .data_i(data_i),
+
+  .empty_o(),
+  .full_o(),
+  .data_o()
+);
+
+string filename;
+initial begin
+`ifdef DUMP_FILE_NAME
+  filename=`DUMP_FILE_NAME;
+`else
+  filename="fifo.lxt2";
+`endif
+  $dumpfile(filename); $dumpvars();
+  clk_i = 0;
+  rst_i = 1'b1;
+  read_i = 0;
+  write_i = 0;
+  data_i = 0;
+end
+
+always #10 clk_i = ~clk_i;
+
+initial begin
+  #15
+
+  for (integer run = 1; run < 3; run++) begin
+  
+    write_i = 1;
+    for (integer addr = 0; addr < 10; addr++) begin
+
+      data_i = (run << 4) | addr;
+      #20
+      ;
+    end
+
+    write_i = 0;
+    read_i = 1;
+
+    for (integer addr = 0; addr < 10; addr++) begin
+      #20
+      ;
+    end
+
+    read_i = 0;
+    #20
+    ;
+  end
+  #100
+  $finish();
+end
+
+endmodule
diff --git a/fizzbuzz.tb.v b/fizzbuzz.tb.v
deleted file mode 100644
index 7855a9b..0000000
--- a/fizzbuzz.tb.v
+++ /dev/null
@@ -1,49 +0,0 @@
-`timescale 1us/1us
-
-module fizzbuzz_tb (
-);
-
-
-logic [7:0] number;
-logic clk_i;
-
-logic [7:0] num_out;
-
-fizzbuzz uut(
-  .num_i(number),
-  .num_o(num_out),
-  .fizz_o(),
-  .buzz_o(),
-  .fizzbuzz_o()
-);
-
-string filename;
-initial begin
-`ifdef DUMP_FILE_NAME
-  filename=`DUMP_FILE_NAME;
-`else
-  filename="fizzbuzz.lxt2";
-`endif
-  $dumpfile(filename); $dumpvars();
-
-
-  clk_i = 0;
-  number = '0;
-end
-
-always #10 begin
-  clk_i = ~clk_i;
-end
-
-always @(negedge clk_i) begin
-  number <= number + 1;
-  // give iverilog some simulation time...
-  #1;
-  if (number == 3) assert(num_out == 0);
-  if (number == 5) assert(num_out == 0);
-  if (number == 15) assert(num_out == 0);
-
-  if (number == 255) $finish;
-end
-
-endmodule
diff --git a/fizzbuzz_tb.v b/fizzbuzz_tb.v
new file mode 100644
index 0000000..2a8cdff
--- /dev/null
+++ b/fizzbuzz_tb.v
@@ -0,0 +1,49 @@
+`timescale 1us/1us
+
+module fizzbuzz_tb (
+);
+
+
+logic [7:0] number;
+logic clk_i;
+
+logic [7:0] num_out;
+
+fizzbuzz uut (
+  .num_i(number),
+  .num_o(num_out),
+  .fizz_o(),
+  .buzz_o(),
+  .fizzbuzz_o()
+);
+
+string filename;
+initial begin
+`ifdef DUMP_FILE_NAME
+  filename=`DUMP_FILE_NAME;
+`else
+  filename="fizzbuzz.lxt2";
+`endif
+  $dumpfile(filename); $dumpvars();
+
+
+  clk_i = 0;
+  number = '0;
+end
+
+always #10 begin
+  clk_i = ~clk_i;
+end
+
+always @(negedge clk_i) begin
+  number <= number + 1;
+  // give iverilog some simulation time...
+  #1;
+  if (number == 3) assert(num_out == 0);
+  if (number == 5) assert(num_out == 0);
+  if (number == 15) assert(num_out == 0);
+
+  if (number == 255) $finish;
+end
+
+endmodule
diff --git a/led_toggle.tb.v b/led_toggle.tb.v
deleted file mode 100644
index a883af4..0000000
--- a/led_toggle.tb.v
+++ /dev/null
@@ -1,60 +0,0 @@
-`timescale 1us/1us
-
-module led_toggle_tb (
-);
-
-logic clk_i;
-logic rst_i;
-logic key_i;
-
-logic [5:0] led;
-
-led_toggle #(.STABLE_PERIOD(2)) uut(
-  .rst_i(rst_i),
-  .clk_i(clk_i),
-  .key_i(key_i),
-  .led(led)
-);
-
-string filename;
-initial begin
-`ifdef DUMP_FILE_NAME
-  filename=`DUMP_FILE_NAME;
-`else
-  filename="led_toggle.lxt2";
-`endif
-  $dumpfile(filename); $dumpvars();
-  clk_i = 0;
-  key_i = 1'b1;
-  #1
-  rst_i = 0;
-  #1
-  rst_i = 1;
-end
-
-always #10 clk_i = ~clk_i;
-
-
-initial begin
-  // initial key press
-  #13
-  key_i = ~key_i;
-  repeat(2) @(negedge clk_i);
-  key_i = ~key_i;
-
-  // try bouncing
-
-  repeat(3) @(negedge clk_i);
-
-  for (integer i=0; i < 19; i = i + 1) begin
-    @(negedge clk_i);
-    key_i = ~key_i;
-  end
-  repeat(10) @(negedge clk_i);
-  key_i = ~key_i;
-
-  repeat(10) @(negedge clk_i);
-  $finish();
-end
-
-endmodule
diff --git a/led_toggle_bouncy.tb.v b/led_toggle_bouncy.tb.v
deleted file mode 100644
index 7999454..0000000
--- a/led_toggle_bouncy.tb.v
+++ /dev/null
@@ -1,51 +0,0 @@
-`timescale 1us/1us
-
-module led_toggle_bouncy_tb (
-);
-
-logic clk_i;
-logic key_i;
-logic [5:0] led;
-
-led_toggle_bouncy uut(
-  .clk_i(clk_i),
-  .key_i(key_i),
-  .led(led)
-);
-
-string filename;
-initial begin
-`ifdef DUMP_FILE_NAME
-  filename=`DUMP_FILE_NAME;
-`else
-  filename="led_toggle_bouncy.lxt2";
-`endif
-  $dumpfile(filename); $dumpvars();
-
-  clk_i = 0;
-  key_i = 1'b1;
-end
-
-always #10 clk_i = ~clk_i;
-
-initial begin
-  // initial key press
-  @(negedge clk_i);
-  key_i = ~key_i;
-  repeat(2) @(negedge clk_i);
-  key_i = ~key_i;
-
-  // try bouncing
-
-  repeat(2) @(negedge clk_i);
-
-  for (integer i=0; i < 20; i = i + 1) begin
-    @(negedge clk_i);
-    key_i = ~key_i;
-  end
-
-  repeat(5) @(negedge clk_i);
-  $finish();
-end
-
-endmodule
diff --git a/led_toggle_bouncy_tb.v b/led_toggle_bouncy_tb.v
new file mode 100644
index 0000000..f300071
--- /dev/null
+++ b/led_toggle_bouncy_tb.v
@@ -0,0 +1,51 @@
+`timescale 1us/1us
+
+module led_toggle_bouncy_tb (
+);
+
+logic clk_i;
+logic key_i;
+logic [5:0] led;
+
+led_toggle_bouncy uut (
+  .clk_i(clk_i),
+  .key_i(key_i),
+  .led(led)
+);
+
+string filename;
+initial begin
+`ifdef DUMP_FILE_NAME
+  filename=`DUMP_FILE_NAME;
+`else
+  filename="led_toggle_bouncy.lxt2";
+`endif
+  $dumpfile(filename); $dumpvars();
+
+  clk_i = 0;
+  key_i = 1'b1;
+end
+
+always #10 clk_i = ~clk_i;
+
+initial begin
+  // initial key press
+  @(negedge clk_i);
+  key_i = ~key_i;
+  repeat(2) @(negedge clk_i);
+  key_i = ~key_i;
+
+  // try bouncing
+
+  repeat(2) @(negedge clk_i);
+
+  for (integer i=0; i < 20; i = i + 1) begin
+    @(negedge clk_i);
+    key_i = ~key_i;
+  end
+
+  repeat(5) @(negedge clk_i);
+  $finish();
+end
+
+endmodule
diff --git a/led_toggle_tb.v b/led_toggle_tb.v
new file mode 100644
index 0000000..f5f4fd5
--- /dev/null
+++ b/led_toggle_tb.v
@@ -0,0 +1,60 @@
+`timescale 1us/1us
+
+module led_toggle_tb (
+);
+
+logic clk_i;
+logic rst_i;
+logic key_i;
+
+logic [5:0] led;
+
+led_toggle #(.STABLE_PERIOD(2)) uut (
+  .rst_i(rst_i),
+  .clk_i(clk_i),
+  .key_i(key_i),
+  .led(led)
+);
+
+string filename;
+initial begin
+`ifdef DUMP_FILE_NAME
+  filename=`DUMP_FILE_NAME;
+`else
+  filename="led_toggle.lxt2";
+`endif
+  $dumpfile(filename); $dumpvars();
+  clk_i = 0;
+  key_i = 1'b1;
+  #1
+  rst_i = 0;
+  #1
+  rst_i = 1;
+end
+
+always #10 clk_i = ~clk_i;
+
+
+initial begin
+  // initial key press
+  #13
+  key_i = ~key_i;
+  repeat(2) @(negedge clk_i);
+  key_i = ~key_i;
+
+  // try bouncing
+
+  repeat(3) @(negedge clk_i);
+
+  for (integer i=0; i < 19; i = i + 1) begin
+    @(negedge clk_i);
+    key_i = ~key_i;
+  end
+  repeat(10) @(negedge clk_i);
+  key_i = ~key_i;
+
+  repeat(10) @(negedge clk_i);
+  $finish();
+end
+
+endmodule
diff --git a/my_mem.tb.v b/my_mem.tb.v
deleted file mode 100644
index c8c2e12..0000000
--- a/my_mem.tb.v
+++ /dev/null
@@ -1,99 +0,0 @@
-// LLM generated, because I'm too lazy to do this manually
-
-`timescale 1us/1ns
-
-module my_mem_tb();
-
-  localparam DATA_WIDTH = 8;
-  localparam DATA_DEPTH = 16;
-  localparam ADDR_WIDTH = $clog2(DATA_DEPTH);
-
-  // DUT signals
-  logic clk;
-  logic write_en_i;
-  logic read_en_i;
-  logic [ADDR_WIDTH-1:0] r_read_addr;
-  logic [ADDR_WIDTH-1:0] r_write_addr;
-  logic [DATA_WIDTH-1:0] data_i;
-  logic [DATA_WIDTH-1:0] data_o;
-
-  // Instantiate DUT
-  my_mem #(
-    .DATA_WIDTH(DATA_WIDTH),
-    .DATA_DEPTH(DATA_DEPTH)
-  ) dut (
-    .clk_i(clk),
-    .write_en_i(write_en_i),
-    .read_en_i(read_en_i),
-    .r_read_addr(r_read_addr),
-    .r_write_addr(r_write_addr),
-    .data_i(data_i),
-    .data_o(data_o)
-  );
-
-  string filename;
-  initial begin
-  `ifdef DUMP_FILE_NAME
-    filename=`DUMP_FILE_NAME;
-  `else
-    filename="my_mem.lxt2";
-  `endif
-    $dumpfile(filename); $dumpvars();
-  end
-
-  // Clock generator
-  always #10 clk = ~clk;
-
-  // Test sequence
-  initial begin
-    clk = 0;
-    write_en_i = 0;
-    read_en_i  = 0;
-    r_read_addr  = '0;
-    r_write_addr = '0;
-    data_i = '0;
-
-    repeat (3) @(negedge clk);
-
-    // -------------------------
-    // Write some values
-    // -------------------------
-    @(negedge clk);
-    write_en_i   = 1;
-    r_write_addr = 10;
-    data_i       = 8'hA5;
-
-    @(negedge clk);
-    r_write_addr = 11;
-    data_i       = 8'h3C;
-
-    @(negedge clk);
-    write_en_i = 0;
-
-    // -------------------------
-    // Read back values
-    // -------------------------
-
-    @(negedge clk);
-    read_en_i   = 1;
-    r_read_addr = 10;
-
-    @(negedge clk);
-    assert (data_o == 8'hA5)
-    else $error("ASSERTION FAILED: addr 10 expected 0xA5, got 0x%02h", data_o);
-
-    @(negedge clk);
-    r_read_addr = 11;
-
-    @(negedge clk);
-    assert (data_o == 8'h3C)
-    else $error("ASSERTION FAILED: addr 11 expected 0x3C, got 0x%02h", data_o);
-
-    @(negedge clk);
-    read_en_i = 0;
-
-    repeat (3) @(negedge clk);
-    $finish;
-  end
-
-endmodule
diff --git a/my_mem_tb.v b/my_mem_tb.v
new file mode 100644
index 0000000..c8c2e12
--- /dev/null
+++ b/my_mem_tb.v
@@ -0,0 +1,99 @@
+// LLM generated, because I'm too lazy to do this manually
+
+`timescale 1us/1ns
+
+module my_mem_tb();
+
+  localparam DATA_WIDTH = 8;
+  localparam DATA_DEPTH = 16;
+  localparam ADDR_WIDTH = $clog2(DATA_DEPTH);
+
+  // DUT signals
+  logic clk;
+  logic write_en_i;
+  logic read_en_i;
+  logic [ADDR_WIDTH-1:0] r_read_addr;
+  logic [ADDR_WIDTH-1:0] r_write_addr;
+  logic [DATA_WIDTH-1:0] data_i;
+  logic [DATA_WIDTH-1:0] data_o;
+
+  // Instantiate DUT
+  my_mem #(
+    .DATA_WIDTH(DATA_WIDTH),
+    .DATA_DEPTH(DATA_DEPTH)
+  ) dut (
+    .clk_i(clk),
+    .write_en_i(write_en_i),
+    .read_en_i(read_en_i),
+    .r_read_addr(r_read_addr),
+    .r_write_addr(r_write_addr),
+    .data_i(data_i),
+    .data_o(data_o)
+  );
+
+  string filename;
+  initial begin
+  `ifdef DUMP_FILE_NAME
+    filename=`DUMP_FILE_NAME;
+  `else
+    filename="my_mem.lxt2";
+  `endif
+    $dumpfile(filename); $dumpvars();
+  end
+
+  // Clock generator
+  always #10 clk = ~clk;
+
+  // Test sequence
+  initial begin
+    clk = 0;
+    write_en_i = 0;
+    read_en_i  = 0;
+    r_read_addr  = '0;
+    r_write_addr = '0;
+    data_i = '0;
+
+    repeat (3) @(negedge clk);
+
+    // -------------------------
+    // Write some values
+    // -------------------------
+    @(negedge clk);
+    write_en_i   = 1;
+    r_write_addr = 10;
+    data_i       = 8'hA5;
+
+    @(negedge clk);
+    r_write_addr = 11;
+    data_i       = 8'h3C;
+
+    @(negedge clk);
+    write_en_i = 0;
+
+    // -------------------------
+    // Read back values
+    // -------------------------
+
+    @(negedge clk);
+    read_en_i   = 1;
+    r_read_addr = 10;
+
+    @(negedge clk);
+    assert (data_o == 8'hA5)
+    else $error("ASSERTION FAILED: addr 10 expected 0xA5, got 0x%02h", data_o);
+
+    @(negedge clk);
+    r_read_addr = 11;
+
+    @(negedge clk);
+    assert (data_o == 8'h3C)
+    else $error("ASSERTION FAILED: addr 11 expected 0x3C, got 0x%02h", data_o);
+
+    @(negedge clk);
+    read_en_i = 0;
+
+    repeat (3) @(negedge clk);
+    $finish;
+  end
+
+endmodule
diff --git a/par_to_ser.tb.v b/par_to_ser.tb.v
deleted file mode 100644
index b610884..0000000
--- a/par_to_ser.tb.v
+++ /dev/null
@@ -1,69 +0,0 @@
-`timescale 1us/1us
-
-module par_to_ser_tb (
-);
-
-logic clk_i;
-logic rst_i;
-logic data_valid_i;
-logic [7:0] dat_i;
-logic dat_o;
-
-par_to_ser uut(
-  .clk_i(clk_i),
-  .rst_i(rst_i),
-  .data_valid_i(data_valid_i),
-  .dat_i(dat_i),
-  .dat_o(dat_o),
-  .dat_valid_o()
-);
-
-string filename;
-initial begin
-`ifdef DUMP_FILE_NAME
-  filename=`DUMP_FILE_NAME;
-`else
-  filename="par_to_ser.lxt2";
-`endif
-  $dumpfile(filename); $dumpvars();
-  clk_i = 0;
-  rst_i = 1'b1;
-  data_valid_i = 1'b0;
-
-  #1
-  rst_i = 1'b0;
-  #1
-  rst_i = 1'b1;
-end
-
-always #10 clk_i = ~clk_i;
-
-bit sollbit = 1'b0;
-
-initial begin
-  #13
-  @(negedge clk_i);
-
-  for (integer i = 0; i < 255; i++) begin
-    // clock data in
-    dat_i = i;
-    data_valid_i = 1'b1;
-
-    @(negedge clk_i);
-    data_valid_i = 1'b0;
-
-    for (integer j = 0; j < 8; j++) begin
-      sollbit = (i >> j) & 1;
-      assert(dat_o == sollbit)
-      else $error("Expected bit to be %d, but was %d", sollbit, dat_o);
-
-      @(negedge clk_i);
-    end
-
-    repeat(2) @(negedge clk_i);
-  end
-
-  $finish();
-end
-
-endmodule
diff --git a/par_to_ser_tb.v b/par_to_ser_tb.v
new file mode 100644
index 0000000..edb1f9b
--- /dev/null
+++ b/par_to_ser_tb.v
@@ -0,0 +1,69 @@
+`timescale 1us/1us
+
+module par_to_ser_tb (
+);
+
+logic clk_i;
+logic rst_i;
+logic data_valid_i;
+logic [7:0] dat_i;
+logic dat_o;
+
+par_to_ser uut (
+  .clk_i(clk_i),
+  .rst_i(rst_i),
+  .data_valid_i(data_valid_i),
+  .dat_i(dat_i),
+  .dat_o(dat_o),
+  .dat_valid_o()
+);
+
+string filename;
+initial begin
+`ifdef DUMP_FILE_NAME
+  filename=`DUMP_FILE_NAME;
+`else
+  filename="par_to_ser.lxt2";
+`endif
+  $dumpfile(filename); $dumpvars();
+  clk_i = 0;
+  rst_i = 1'b1;
+  data_valid_i = 1'b0;
+
+  #1
+  rst_i = 1'b0;
+  #1
+  rst_i = 1'b1;
+end
+
+always #10 clk_i = ~clk_i;
+
+bit sollbit = 1'b0;
+
+initial begin
+  #13
+  @(negedge clk_i);
+
+  for (integer i = 0; i < 255; i++) begin
+    // clock data in
+    dat_i = i;
+    data_valid_i = 1'b1;
+
+    @(negedge clk_i);
+    data_valid_i = 1'b0;
+
+    for (integer j = 0; j < 8; j++) begin
+      sollbit = (i >> j) & 1;
+      assert(dat_o == sollbit)
+      else $error("Expected bit to be %d, but was %d", sollbit, dat_o);
+
+      @(negedge clk_i);
+    end
+
+    repeat(2) @(negedge clk_i);
+  end
+
+  $finish();
+end
+
+endmodule
diff --git a/par_to_ser_to_par.tb.v b/par_to_ser_to_par.tb.v
deleted file mode 100644
index c422d86..0000000
--- a/par_to_ser_to_par.tb.v
+++ /dev/null
@@ -1,82 +0,0 @@
-// converts back and forth
-// parallel > serial > parallel
-
-`timescale 1us/1us
-
-module par_to_ser_to_par_tb (
-);
-
-logic clk_i;
-logic rst_i;
-logic data_valid_i;
-logic [7:0] dat_i;
-
-logic dat_o;
-logic [7:0] dat_o2;
-logic send_valid;
-
-par_to_ser uut (
-  .clk_i(clk_i),
-  .rst_i(rst_i),
-  .data_valid_i(data_valid_i),
-  .dat_i(dat_i),
-  .dat_o(dat_o),
-  .dat_valid_o(send_valid)
-);
-
-ser_to_par uut2 (
-  .clk_i(clk_i),
-  .rst_i(rst_i),
-
-  .dat_valid_i(send_valid),
-  .dat_i(dat_o),
-
-  .dat_o(dat_o2),
-  .dat_valid_o()
-);
-
-string filename;
-initial begin
-`ifdef DUMP_FILE_NAME
-  filename=`DUMP_FILE_NAME;
-`else
-  filename="par_to_ser_to_par.lxt2";
-`endif
-  $dumpfile(filename); $dumpvars();
-  clk_i = 0;
-  rst_i = 1'b1;
-  data_valid_i = 1'b0;
-
-  #1
-  rst_i = 1'b0;
-  #1
-  rst_i = 1'b1;
-end
-
-always #10 clk_i = ~clk_i;
-
-initial begin
-  #13;
-  @(negedge clk_i);
-
-  for (integer i = 0; i < 255; i++) begin
-    // clock data in
-    dat_i = i;
-    data_valid_i = 1'b1;
-
-    // wait 1 cycle
-    @(negedge clk_i);
-    data_valid_i = 1'b0;
-
-    // let module do its work
-    repeat(10) @(negedge clk_i);
-  
-    assert(i == dat_o2)
-    else $error("Expected output to be h%x, but was h%x", i, dat_o2);
-
-  end
-
-  $finish();
-end
-
-endmodule
diff --git a/par_to_ser_to_par_tb.v b/par_to_ser_to_par_tb.v
new file mode 100644
index 0000000..c422d86
--- /dev/null
+++ b/par_to_ser_to_par_tb.v
@@ -0,0 +1,82 @@
+// converts back and forth
+// parallel > serial > parallel
+
+`timescale 1us/1us
+
+module par_to_ser_to_par_tb (
+);
+
+logic clk_i;
+logic rst_i;
+logic data_valid_i;
+logic [7:0] dat_i;
+
+logic dat_o;
+logic [7:0] dat_o2;
+logic send_valid;
+
+par_to_ser uut (
+  .clk_i(clk_i),
+  .rst_i(rst_i),
+  .data_valid_i(data_valid_i),
+  .dat_i(dat_i),
+  .dat_o(dat_o),
+  .dat_valid_o(send_valid)
+);
+
+ser_to_par uut2 (
+  .clk_i(clk_i),
+  .rst_i(rst_i),
+
+  .dat_valid_i(send_valid),
+  .dat_i(dat_o),
+
+  .dat_o(dat_o2),
+  .dat_valid_o()
+);
+
+string filename;
+initial begin
+`ifdef DUMP_FILE_NAME
+  filename=`DUMP_FILE_NAME;
+`else
+  filename="par_to_ser_to_par.lxt2";
+`endif
+  $dumpfile(filename); $dumpvars();
+  clk_i = 0;
+  rst_i = 1'b1;
+  data_valid_i = 1'b0;
+
+  #1
+  rst_i = 1'b0;
+  #1
+  rst_i = 1'b1;
+end
+
+always #10 clk_i = ~clk_i;
+
+initial begin
+  #13;
+  @(negedge clk_i);
+
+  for (integer i = 0; i < 255; i++) begin
+    // clock data in
+    dat_i = i;
+    data_valid_i = 1'b1;
+
+    // wait 1 cycle
+    @(negedge clk_i);
+    data_valid_i = 1'b0;
+
+    // let module do its work
+    repeat(10) @(negedge clk_i);
+  
+    assert(i == dat_o2)
+    else $error("Expected output to be h%x, but was h%x", i, dat_o2);
+
+  end
+
+  $finish();
+end
+
+endmodule
diff --git a/ser_to_par.tb.v b/ser_to_par.tb.v
deleted file mode 100644
index de730c6..0000000
--- a/ser_to_par.tb.v
+++ /dev/null
@@ -1,63 +0,0 @@
-`timescale 1us/1us
-
-module ser_to_par_tb (
-);
-
-logic clk_i;
-logic rst_i;
-logic dat_i;
-logic dat_valid;
-logic [7:0] dat_o;
-
-ser_to_par uut(
-  .clk_i(clk_i),
-  .rst_i(rst_i),
-  .dat_i(dat_i),
-  .dat_o(dat_o),
-  .dat_valid_i(dat_valid),
-  .dat_valid_o()
-);
-
-string filename;
-initial begin
-`ifdef DUMP_FILE_NAME
-  filename=`DUMP_FILE_NAME;
-`else
-  filename="ser_to_par.lxt2";
-`endif
-  $dumpfile(filename); $dumpvars();
-  clk_i = 0;
-  rst_i = 1'b1;
-  dat_i = 1'b1;
-  dat_valid= 1'b0;
-  #1
-  rst_i = 0;
-  #1
-  rst_i = 1;
-end
-
-always #10 clk_i = ~clk_i;
-
-initial begin
-  #13;
-  @(negedge clk_i);
-
-  dat_valid = 1'b1;
-  // start data
-  dat_i = 1'b0;
-  @(negedge clk_i);
-  // - 1 clk cycle, 1 bit later:
-  dat_i = 1'b1;
-
-  repeat (7) @(negedge clk_i);
-  dat_valid = 1'b0;
-
-  // - 7 clk cycle, 7 bits later:
-  assert (dat_o == 8'hfe)
-  else $error("Excected dat_o to be hfe, was h%x", dat_o);
-
-  @(negedge clk_i);
-  $finish();
-end
-
-endmodule
diff --git a/ser_to_par_tb.v b/ser_to_par_tb.v
new file mode 100644
index 0000000..e82b56e
--- /dev/null
+++ b/ser_to_par_tb.v
@@ -0,0 +1,63 @@
+`timescale 1us/1us
+
+module ser_to_par_tb (
+);
+
+logic clk_i;
+logic rst_i;
+logic dat_i;
+logic dat_valid;
+logic [7:0] dat_o;
+
+ser_to_par uut (
+  .clk_i(clk_i),
+  .rst_i(rst_i),
+  .dat_i(dat_i),
+  .dat_o(dat_o),
+  .dat_valid_i(dat_valid),
+  .dat_valid_o()
+);
+
+string filename;
+initial begin
+`ifdef DUMP_FILE_NAME
+  filename=`DUMP_FILE_NAME;
+`else
+  filename="ser_to_par.lxt2";
+`endif
+  $dumpfile(filename); $dumpvars();
+  clk_i = 0;
+  rst_i = 1'b1;
+  dat_i = 1'b1;
+  dat_valid= 1'b0;
+  #1
+  rst_i = 0;
+  #1
+  rst_i = 1;
+end
+
+always #10 clk_i = ~clk_i;
+
+initial begin
+  #13;
+  @(negedge clk_i);
+
+  dat_valid = 1'b1;
+  // start data
+  dat_i = 1'b0;
+  @(negedge clk_i);
+  // - 1 clk cycle, 1 bit later:
+  dat_i = 1'b1;
+
+  repeat (7) @(negedge clk_i);
+  dat_valid = 1'b0;
+
+  // - 7 clk cycle, 7 bits later:
+  assert (dat_o == 8'hfe)
+  else $error("Excected dat_o to be hfe, was h%x", dat_o);
+
+  @(negedge clk_i);
+  $finish();
+end
+
+endmodule
diff --git a/template.tb.v b/template.tb.v
deleted file mode 100644
index fb37668..0000000
--- a/template.tb.v
+++ /dev/null
@@ -1,37 +0,0 @@
-`timescale 1us/1us
-
-module template_tb (
-);
-
-reg clk_i;
-reg rst_i;
-
-template uut(
-  .clk_i(clk_i),
-  .rst_i(rst_i)
-);
-
-string filename;
-initial begin
-`ifdef DUMP_FILE_NAME
-  filename=`DUMP_FILE_NAME;
-`else
-  filename="template.lxt2";
-`endif
-  $dumpfile(filename); $dumpvars();
-  clk_i <= 0;
-  rst_i <= 1'b1;
-
-end
-
-always #10 clk_i = ~clk_i;
-
-initial begin
-  #13
-  @(negedge clk_i);
-
-  #100
-  $finish();
-end
-
-endmodule
diff --git a/template_tb.v b/template_tb.v
new file mode 100644
index 0000000..3526168
--- /dev/null
+++ b/template_tb.v
@@ -0,0 +1,37 @@
+`timescale 1us/1us
+
+module template_tb (
+);
+
+reg clk_i;
+reg rst_i;
+
+template uut (
+  .clk_i(clk_i),
+  .rst_i(rst_i)
+);
+
+string filename;
+initial begin
+`ifdef DUMP_FILE_NAME
+  filename=`DUMP_FILE_NAME;
+`else
+  filename="template.lxt2";
+`endif
+  $dumpfile(filename); $dumpvars();
+  clk_i = 0;
+  rst_i = 1'b1;
+
+end
+
+always #10 clk_i = ~clk_i;
+
+initial begin
+  #13
+  @(negedge clk_i);
+
+  #100
+  $finish();
+end
+
+endmodule
diff --git a/tst_delay.tb.v b/tst_delay.tb.v
deleted file mode 100644
index 41a133a..0000000
--- a/tst_delay.tb.v
+++ /dev/null
@@ -1,50 +0,0 @@
-// try to figure out how iverilog samples edges
-`timescale 1us/1us
-
-module tst_delay_tb (
-);
-
-reg clk_i;
-reg data_i;
-wire data_o;
-
-tst_delay uut(
-  .clk_i(clk_i),
-  .data_i(data_i),
-  .data_o(data_o)
-);
-
-string filename;
-initial begin
-`ifdef DUMP_FILE_NAME
-  filename=`DUMP_FILE_NAME;
-`else
-  filename="tst_delay.lxt2";
-`endif
-  $dumpfile(filename); $dumpvars();
-  clk_i = 0;
-  data_i = 0;
-end
-
-always #10 clk_i = ~clk_i;
-
-initial begin
-  #9
-  data_i = 1;
-  #2
-  data_i = 0;
-  // note the <= assignment
-  #19
-  data_i <= 1;
-  #1
-  data_i = 0;
-  // note the = assignment
-  #19
-  data_i = 1;
-  #1
-  data_i = 0;
-  #40
-  $finish();
-end
-
-endmodule
diff --git a/tst_delay_tb.v b/tst_delay_tb.v
new file mode 100644
index 0000000..03ef185
--- /dev/null
+++ b/tst_delay_tb.v
@@ -0,0 +1,54 @@
+// try to figure out how iverilog samples edges
+`timescale 1us/1us
+
+module tst_delay_tb (
+);
+
+reg clk_i;
+reg data_i;
+wire data_o;
+
+tst_delay uut (
+  .clk_i(clk_i),
+  .data_i(data_i),
+  .data_o(data_o)
+);
+
+string filename;
+initial begin
+`ifdef DUMP_FILE_NAME
+  filename=`DUMP_FILE_NAME;
+`else
+  filename="tst_delay.lxt2";
+`endif
+  $dumpfile(filename); $dumpvars();
+  clk_i = 0;
+  data_i = 0;
+end
+
+always #10 clk_i = ~clk_i;
+
+initial begin
+  #9
+  data_i = 1;
+  #2
+  data_i = 0;
+
+  /* verilator lint_off INITIALDLY */
+  // note the <= assignment
+  #19
+  data_i <= 1;
+  /* verilator lint_on INITIALDLY */
+
+  #1
+  data_i = 0;
+  // note the = assignment
+  #19
+  data_i = 1;
+  #1
+  data_i = 0;
+  #40
+  $finish();
+end
+
+endmodule
-- 
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