From fa5951db0ab2fcc9a9dfd6165e0e6c631df46c07 Mon Sep 17 00:00:00 2001
From: uvok
Date: Fri, 26 Dec 2025 20:22:48 +0100
Subject: p2s: Fix logic and reset initialization

also, don't use blocking assignments
---
 par_to_ser.v | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/par_to_ser.v b/par_to_ser.v
index 87f9a0e..6b2e375 100644
--- a/par_to_ser.v
+++ b/par_to_ser.v
@@ -21,18 +21,19 @@ reg [7:0] send_data = 8'hff;
 always @(posedge clk_i or negedge rst_i) begin
   if (!rst_i) begin
     dat_o <= 1'b1;
+    sending <= 1'b0;
+    send_data <= 8'hff;
   end else if (data_valid_i && !sending) begin
     sending <= 1;
-    dat_o = dat_i[0];
-    send_data[6:0] <= dat_i[7:1];
+    dat_o <= dat_i[0];
+    send_data <= {1'b1, dat_i[7:1]};
   end else if (!data_valid_i) begin
     sending <= 1'b0;
-    dat_o = 1'b1;
+    dat_o <= 1'b1;
   end else if (sending) begin
-    dat_o = send_data[0];
-    send_data[6:0] <= send_data[7:1];
+    dat_o <= send_data[0];
     // arbitrary decision: register is filled with a 1
-    send_data[7] = 1'b1;
+    send_data <= {1'b1, send_data[7:1]};
   end
 end
 
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