From d0a372c3112b28ff3b1bf03ff4a7a0e5a3cafe8e Mon Sep 17 00:00:00 2001
From: uvok
Date: Tue, 30 Dec 2025 10:21:27 +0100
Subject: linting, use different naming

use _tb.v instead of .tb.v,
to stop verilator from shouting
the module name doesn't
match
---
 Makefile | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'Makefile')

diff --git a/Makefile b/Makefile
index 06a693a..94c301c 100644
--- a/Makefile
+++ b/Makefile
@@ -96,14 +96,14 @@ lint: $(PROGRAM).v
 %.lxt2: %.vvp
 	./$< -lxt2
 
-%.vvp: %.v %.tb.v
-	iverilog -DDUMP_FILE_NAME='"$*.lxt2"' -g2012 -o $*.vvp $*.v $*.tb.v
+%.vvp: %.v %_tb.v
+	iverilog -DDUMP_FILE_NAME='"$*.lxt2"' -g2012 -o $*.vvp $*.v $*_tb.v
 
 # verilog unfortunately exits on any warning
 # also on warnings "boohoo, you specified timings in some modules and not in others"
 # since this is fucking annoying, I choose to ignore the exit code.
-verilator.%: %.v %.tb.v
-	verilator --quiet -DDUMP_FILE_NAME='"dump.vvp"' --trace --timing --main --exe --Mdir verilator.$(PROGRAM) $(PROGRAM).tb.v || true
+verilator.%: %.v %_tb.v
+	verilator --quiet -DDUMP_FILE_NAME='"dump.vvp"' --trace --timing --main --exe --Mdir verilator.$(*) $(*)_tb.v || true
 
 # need to specify RM for some reason
 # verilators makefiles doesn't specify the variable
-- 
cgit v1.2.3