From e0970b34d629eb765e6e488f6c43caef1620faf3 Mon Sep 17 00:00:00 2001
From: uvok
Date: Tue, 23 Dec 2025 19:37:13 +0100
Subject: Add FPGA basics

---
 Makefile | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 Makefile

(limited to 'Makefile')

diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..949996d
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,19 @@
+all: led.fs
+
+tangnano9k.cst:
+	wget https://github.com/YosysHQ/apicula/raw/refs/heads/master/examples/tangnano9k.cst || \
+	curl -LO https://github.com/YosysHQ/apicula/raw/refs/heads/master/examples/tangnano9k.cst
+
+led.json: led.v
+	yosys -p "read_verilog led.v; synth_gowin -top led -json led.json"
+
+pnrled.json: tangnano9k.cst led.json
+	nextpnr-himbaechel --json led.json --write pnrled.json \
+	--device GW1NR-LV9QN88PC6/I5 --vopt family=GW1N-9C \
+	--vopt cst=tangnano9k.cst
+
+led.fs: pnrled.json
+	gowin_pack -d GW1N-9C -o led.fs pnrled.json
+
+flash: led.fs
+	openFPGALoader -b tangnano9k -f led.fs
-- 
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