From 138eb3e6bc175e6675f22702b09bd8756b317003 Mon Sep 17 00:00:00 2001
From: uvok
Date: Tue, 6 Jan 2026 19:46:26 +0100
Subject: Documentation

---
 README.txt | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

(limited to 'README.txt')

diff --git a/README.txt b/README.txt
index 18c6ece..0865867 100644
--- a/README.txt
+++ b/README.txt
@@ -1,3 +1,10 @@
+This is a collection of Verilog files.
+Written as I'm learning about the language and FPGAs.
+
+Contents:
+- This directory
+- nandgame: Implementation of the nandgame.com CPU
+
 Learnings:
 
 - Anything that needs to "store" a state must be a reg?
@@ -18,10 +25,14 @@ Questions:
 - Does yosys and other tools "automatically" determine the
   "perfect" wire/register (bus) width if I just specify e.g.
   wire BLA = 1374;
-  ?
+  - Nope, that's a single bit, it will be truncated
 - The book tasked me with writing a serial-to-parallel and parallel-to-serial converter.
   But I think I wrote it "wrong"?
   If I used this in the real world, and chained both components together,
   things would go wrong. as the output is flipped at the rising clock
   edge - violating timings and leading to unpredictable behavior?
   Or not?
+  - nope, synthesis tools "take care of and check" timing.
+    It "somehow just works".
+    Or rather, stuff is delayed by one clock cycle, e.g.
+    when chaining flip-flops together.
-- 
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