From 157a4074b3ffaf80564bba1cf74f3b25c87ee6c5 Mon Sep 17 00:00:00 2001
From: uvok
Date: Wed, 24 Dec 2025 19:35:56 +0100
Subject: Document clock freq

---
 README.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'README.txt')

diff --git a/README.txt b/README.txt
index 63529e3..7d8c29e 100644
--- a/README.txt
+++ b/README.txt
@@ -3,4 +3,4 @@ Learnings:
 - Anything that needs to "store" a state must be a reg?
   => wire's can't be assigned in always blocks, yosys complains
 - regs must not lead to wires? (unsure where I read that)
-
+- Clock on the tang9k is 27 MHz
-- 
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