From 4eb00254cf157d041ee2ab1babbaa39c2a23443c Mon Sep 17 00:00:00 2001
From: uvok
Date: Fri, 26 Dec 2025 12:52:59 +0100
Subject: Update README

---
 README.txt | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'README.txt')

diff --git a/README.txt b/README.txt
index 014cea5..fd579e2 100644
--- a/README.txt
+++ b/README.txt
@@ -3,9 +3,15 @@ Learnings:
 - Anything that needs to "store" a state must be a reg?
   => wire's can't be assigned in always blocks, yosys complains
 - regs must not lead to wires? (unsure where I read that)
+  - https://blog.waynejohnson.net/doku.php/verilog_wire_and_reg
+  -> wires of an outer module can be connecting to an inner module.
+  -> reg can be input to an inner module
+  -> regs can't be outputs
 - Clock on the tang9k is 27 MHz
 
 Questions:
 
 - Why do so many examples use always @(posedge clk or nededge rst).
   i.e., why is the clk always included?
+  - "async reset" - asynchronous events might be missed, and they
+    don't work well with clocked registers.
\ No newline at end of file
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