From 8162447f44247bcde09d163fc9ac31b00ac26a8b Mon Sep 17 00:00:00 2001
From: uvok
Date: Thu, 25 Dec 2025 12:44:30 +0100
Subject: Questions

---
 README.txt | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'README.txt')

diff --git a/README.txt b/README.txt
index 7d8c29e..014cea5 100644
--- a/README.txt
+++ b/README.txt
@@ -4,3 +4,8 @@ Learnings:
   => wire's can't be assigned in always blocks, yosys complains
 - regs must not lead to wires? (unsure where I read that)
 - Clock on the tang9k is 27 MHz
+
+Questions:
+
+- Why do so many examples use always @(posedge clk or nededge rst).
+  i.e., why is the clk always included?
-- 
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