From b9b169fd0524741217a81d5b6169e2531a8f4815 Mon Sep 17 00:00:00 2001
From: uvok
Date: Fri, 26 Dec 2025 18:48:27 +0100
Subject: Add question

---
 README.txt | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

(limited to 'README.txt')

diff --git a/README.txt b/README.txt
index 1445c46..18c6ece 100644
--- a/README.txt
+++ b/README.txt
@@ -18,4 +18,10 @@ Questions:
 - Does yosys and other tools "automatically" determine the
   "perfect" wire/register (bus) width if I just specify e.g.
   wire BLA = 1374;
-  ?
\ No newline at end of file
+  ?
+- The book tasked me with writing a serial-to-parallel and parallel-to-serial converter.
+  But I think I wrote it "wrong"?
+  If I used this in the real world, and chained both components together,
+  things would go wrong. as the output is flipped at the rising clock
+  edge - violating timings and leading to unpredictable behavior?
+  Or not?
-- 
cgit v1.2.3