From a5115147fbe0661ca78702e97b0fa3d5277ac83c Mon Sep 17 00:00:00 2001
From: uvok
Date: Wed, 24 Dec 2025 15:57:40 +0100
Subject: Make clock divider separate module

---
 clkdiv.v | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)
 create mode 100644 clkdiv.v

(limited to 'clkdiv.v')

diff --git a/clkdiv.v b/clkdiv.v
new file mode 100644
index 0000000..aef93eb
--- /dev/null
+++ b/clkdiv.v
@@ -0,0 +1,31 @@
+module clkdiv (
+    input rst_i,
+    input clk,              // clk input
+    output o_divclk
+);
+
+reg [23:0] counter;
+
+always @(posedge clk or negedge rst_i) begin
+    if (!rst_i)
+        counter <= 24'd0;
+//    else if (counter < 24'd1349_9999)       // 0.5s delay
+    else if (counter < 24'd674_9999)       // 0.5s delay
+        counter <= counter + 1'b1;
+    else
+        counter <= 24'd0;
+end
+
+always @(posedge clk or negedge rst_i) begin
+    if (!rst_i)
+        o_divclk <= 1'b0;
+//    else if (counter == 24'd1349_9999)       // 0.5s delay
+    else if (counter == 24'd674_9999)       // 0.5s delay
+        o_divclk[0] <= o_divclk[0] + 1;
+    else
+        o_divclk <= o_divclk;
+end
+
+
+endmodule
+
-- 
cgit v1.2.3