From 87049a63ca2a2018fa3fdb720b8993413619755f Mon Sep 17 00:00:00 2001
From: uvok
Date: Tue, 30 Dec 2025 10:06:10 +0100
Subject: Fix testbench

---
 debounce.tb.v | 53 ++++++++++++++++++++++++++++-------------------------
 1 file changed, 28 insertions(+), 25 deletions(-)

(limited to 'debounce.tb.v')

diff --git a/debounce.tb.v b/debounce.tb.v
index ba90aa7..3376434 100644
--- a/debounce.tb.v
+++ b/debounce.tb.v
@@ -3,10 +3,10 @@
 module debounce_tb (
 );
 
-reg rst_i;
-reg clk_i;
-reg signal_i;
-wire signal_o;
+logic rst_i;
+logic clk_i;
+logic signal_i;
+logic signal_o;
 
 integer i = 0;
 
@@ -26,48 +26,51 @@ initial begin
 `endif
   $dumpfile(filename); $dumpvars();
 
-  clk_i <= 0;
-  rst_i <= 1'b1;
-  signal_i <= 1'b1;
-  #4
-  rst_i <= 1'b0;
-  #4
-  rst_i <= 1'b1;
+  clk_i = 0;
+  rst_i = 1'b1;
+  signal_i = 1'b1;
+  #1
+  rst_i = 1'b0;
+  #1
+  rst_i = 1'b1;
 end
 
 always #10 clk_i = ~clk_i;
 
 initial begin
   // initial key press
-  #25
-  signal_i <= ~signal_i;
+  @(negedge clk_i);
+  signal_i = ~signal_i;
   assert (signal_o == 1'b1);
-  #40
-  signal_i <= ~signal_i;
+ 
+  repeat(2) @(negedge clk_i);
+ 
+  signal_i = ~signal_i;
   assert (signal_o == 1'b1);
 
   // try bouncing
 
-  #50
+  repeat(2) @(negedge clk_i);
 
   for (i=0; i < 20; i = i + 1) begin
-    #20
-    signal_i <= ~signal_i;
+    @(negedge clk_i);
+    signal_i = ~signal_i;
     assert (signal_o == 1'b1);
   end
-  #20
-  signal_i <= ~signal_i;
+  @(negedge clk_i);
+  signal_i = ~signal_i;
   assert (signal_o == 1'b1);
-  #200
+
+  repeat(10) @(negedge clk_i);
   assert (signal_o == 1'b0);
 
-  #300
-  signal_i <= ~signal_i;
+  repeat(10) @(negedge clk_i);
+  signal_i = ~signal_i;
 
-  #200
+  repeat(10) @(negedge clk_i);
   assert (signal_o == 1'b1);
 
-  #300
+  repeat(10) @(negedge clk_i);
   $finish();
 end
 
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