From 86901bfbbdd54e1262489fbeaa144394f3abb3fd Mon Sep 17 00:00:00 2001
From: uvok
Date: Fri, 16 Jan 2026 14:22:26 +0100
Subject: eater: Add ALU

while doing so,
add always_out port for regs
---
 eater_cpu/bus_writer.sv | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

(limited to 'eater_cpu/bus_writer.sv')

diff --git a/eater_cpu/bus_writer.sv b/eater_cpu/bus_writer.sv
index 6104301..bbe7a0c 100644
--- a/eater_cpu/bus_writer.sv
+++ b/eater_cpu/bus_writer.sv
@@ -1,3 +1,7 @@
+// Debugging the Ben Eater bus, by manually writing data to it.
+
+`timescale 1us/1us
+
 module bus_writer (
     input [7:0] in_value,
     input in_write_to_output,
@@ -6,4 +10,4 @@ module bus_writer (
 
 assign out_value = in_write_to_output ? in_value : 8'bZ;
 
-endmodule
\ No newline at end of file
+endmodule
-- 
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