From 08736d0ca2bc9abe56ce0a306ebaa58021ae7f0e Mon Sep 17 00:00:00 2001
From: uvok
Date: Thu, 15 Jan 2026 18:44:31 +0100
Subject: Add 1st sketch of eater cpu

---
 eater_cpu/eater_computer.sv | 52 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)
 create mode 100644 eater_cpu/eater_computer.sv

(limited to 'eater_cpu/eater_computer.sv')

diff --git a/eater_cpu/eater_computer.sv b/eater_cpu/eater_computer.sv
new file mode 100644
index 0000000..405d3ff
--- /dev/null
+++ b/eater_cpu/eater_computer.sv
@@ -0,0 +1,52 @@
+// represents the Ben Eater 8bit computer
+
+`timescale 1us/1us
+
+module eater_computer;
+logic clk_in;
+
+/* verilator public_on */
+tri [7:0] bus;
+logic A_to_bus, bus_to_A,
+      B_to_bus, bus_to_B
+;
+/* verilator public_off */
+
+eater_register A (
+  .clk_i(clk_in),
+  .en_store_i(bus_to_A),
+  .en_output_i(A_to_bus),
+  .data_i(bus),
+  .data_o(bus)
+);
+
+eater_register B (
+  .clk_i(clk_in),
+  .en_store_i(bus_to_B),
+  .en_output_i(B_to_bus),
+  .data_i(bus),
+  .data_o(bus)
+);
+
+`ifdef VERILATOR
+initial begin
+  $dumpfile("simpc.vvp");
+  $dumpvars();
+
+  A_to_bus = 0;
+  B_to_bus = 0;
+  bus_to_A = 0;
+  bus_to_B = 0;
+  clk_in = 0;
+end
+
+always #2 clk_in = ~clk_in;
+
+initial begin
+
+  #10
+  $finish();
+end
+`endif
+
+endmodule
-- 
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