From 7daca3a26c3a6d81610fead41248cb5f38e103e8 Mon Sep 17 00:00:00 2001
From: uvok
Date: Sat, 17 Jan 2026 20:04:49 +0100
Subject: eater: Add PC, fix signals for MEM/ADR, add readme

---
 eater_cpu/eater_computer.sv | 68 ++++++++++++++++++++++++++++-----------------
 1 file changed, 42 insertions(+), 26 deletions(-)

(limited to 'eater_cpu/eater_computer.sv')

diff --git a/eater_cpu/eater_computer.sv b/eater_cpu/eater_computer.sv
index 1e618d1..4c59697 100644
--- a/eater_cpu/eater_computer.sv
+++ b/eater_cpu/eater_computer.sv
@@ -2,29 +2,29 @@
 
 `timescale 1us/1us
 
-// fucking being including so that VScode extensions find this module
-//     (because config'ing the include path alone doesn't help)
-// vs fucking actually compiling it and tools complaining about the fucking timescale.
-`ifndef COMPILING
-`include "../playground/my_mem.v"
-`endif
-
 module eater_computer(
   input wire clk_in,
   output wire [7:0] debug_bus
 );
 
 /* verilator public_on */
-tri [7:0] bus, A_out, B_out, RAM_out;
+tri [7:0] bus,
+      A_out,
+      B_out,
+      RAM_out,
+      INS_out
+;
+tri [3:0] PC_out;
+
 logic A_to_bus, bus_to_A,
       B_to_bus, bus_to_B,
       INS_to_bus, bus_to_INS,
       RAM_to_bus, bus_to_RAM,
-      ALU_to_bus
+      ALU_to_bus,
+      PC_to_bus, bus_to_PC,
+      bus_to_MAR
 ;
 
-assign bus = RAM_to_bus ? RAM_out : 8'bz;
-
 assign debug_bus = bus;
 /* verilator public_off */
 
@@ -48,48 +48,50 @@ eater_register B (
   // .data(bus)
 );
 
-tri [7:0] ins_bus_out;
-assign bus[3:0] = ins_bus_out[3:0];
+assign bus[3:0] = INS_out[3:0];
 
 eater_register INS (
   .clk_in(clk_in),
   .en_store_in(bus_to_INS),
   .en_output_in(INS_to_bus),
   .data_in(bus),
-  .bus_out(ins_bus_out),
+  .bus_out(INS_out),
   .always_out()
-  // .data(ins_bus_out)
+  // .data(INS_out)
 );
 
-tri [7:0] mem_adr_bus_out;
-tri [3:0] adr_RAM_in = mem_adr_bus_out[3:0];
+tri [7:0] MEM_ADR_out;
+tri [3:0] RAM_adr_in = MEM_ADR_out[3:0];
 
 eater_register MEM_ADR (
   .clk_in(clk_in),
-  .en_store_in(bus_to_INS),
-  .en_output_in(INS_to_bus),
+  .en_store_in(bus_to_MAR),
+  .en_output_in(1'b0),
   .data_in(bus),
-  .bus_out(mem_adr_bus_out),
-  .always_out()
+  .bus_out(),
+  .always_out(MEM_ADR_out)
   // .data(mem_adr_bus_out)
 );
 
-// Eater RAM is sync???
+// Eater RAM is "technically" synchronous, but still enables write on clk&w_en.
+// However, "my RAM" *always outputs something*, and that's bad.
 my_mem #(
   .DATA_WIDTH(8),
   .DATA_DEPTH(16)
 ) RAM (
   .clk_i(clk_in),
   .write_en_i(bus_to_RAM),
-  // ???
-  .read_en_i(RAM_to_bus),
-  .r_read_addr(adr_RAM_in),
-  .r_write_addr(adr_RAM_in),
+  // doesn't matter
+  .read_en_i(),
+  .r_read_addr(RAM_adr_in),
+  .r_write_addr(RAM_adr_in),
   .data_i(bus),
   .data_o(),
   .async_data_o(RAM_out)
 );
 
+assign bus = RAM_to_bus ? RAM_out : 8'bz;
+
 eater_alu alu (
   .clk_in(clk_in),
   .en_output_in(ALU_to_bus),
@@ -99,4 +101,18 @@ eater_alu alu (
   .bus_out(bus)
 );
 
+tri [3:0] PC_in;
+assign PC_in = bus[3:0];
+
+counter #(
+  .DATA_WIDTH(4)
+) PC (
+  .clk_in(clk_in),
+  .counter_out(PC_out),
+  .X_in(PC_in),
+  .st_store_X_in(bus_to_PC)
+);
+
+assign bus[3:0] = PC_to_bus ? PC_out[3:0] : 4'bz;
+
 endmodule
-- 
cgit v1.2.3