From 86901bfbbdd54e1262489fbeaa144394f3abb3fd Mon Sep 17 00:00:00 2001
From: uvok
Date: Fri, 16 Jan 2026 14:22:26 +0100
Subject: eater: Add ALU

while doing so,
add always_out port for regs
---
 eater_cpu/eater_computer.sv | 46 ++++++++++++++++++++++++++++-----------------
 1 file changed, 29 insertions(+), 17 deletions(-)

(limited to 'eater_cpu/eater_computer.sv')

diff --git a/eater_cpu/eater_computer.sv b/eater_cpu/eater_computer.sv
index cace515..4f1aba2 100644
--- a/eater_cpu/eater_computer.sv
+++ b/eater_cpu/eater_computer.sv
@@ -8,30 +8,33 @@ module eater_computer(
 logic clk_in;
 
 /* verilator public_on */
-tri [7:0] bus;
+tri [7:0] bus, A_out, B_out;
 logic A_to_bus, bus_to_A,
       B_to_bus, bus_to_B,
-      INS_to_bus, bus_to_INS
+      INS_to_bus, bus_to_INS,
+      ALU_to_bus
 ;
 
 assign debug_bus = bus;
 /* verilator public_off */
 
 eater_register A (
-  .clk_i(clk_in),
-  .en_store_i(bus_to_A),
-  .en_output_i(A_to_bus),
-  .data_i(bus),
-  .data_o(bus)
+  .clk_in(clk_in),
+  .en_store_in(bus_to_A),
+  .en_output_in(A_to_bus),
+  .data_in(bus),
+  .bus_out(bus),
+  .always_out(A_out)
   // .data(bus)
 );
 
 eater_register B (
-  .clk_i(clk_in),
-  .en_store_i(bus_to_B),
-  .en_output_i(B_to_bus),
-  .data_i(bus),
-  .data_o(bus)
+  .clk_in(clk_in),
+  .en_store_in(bus_to_B),
+  .en_output_in(B_to_bus),
+  .data_in(bus),
+  .bus_out(bus),
+  .always_out(B_out)
   // .data(bus)
 );
 
@@ -39,14 +42,23 @@ tri [7:0] ins_bus_out;
 assign bus[3:0] = ins_bus_out[3:0];
 
 eater_register INS (
-  .clk_i(clk_in),
-  .en_store_i(bus_to_INS),
-  .en_output_i(INS_to_bus),
-  .data_i(bus),
-  .data_o(ins_bus_out)
+  .clk_in(clk_in),
+  .en_store_in(bus_to_INS),
+  .en_output_in(INS_to_bus),
+  .data_in(bus),
+  .bus_out(ins_bus_out),
+  .always_out()
   // .data(ins_bus_out)
 );
 
+eater_alu alu (
+  .clk_in(clk_in),
+  .en_output_in(ALU_to_bus),
+  .A_in(A_out),
+  .B_in(B_out),
+  .bus_out(bus)
+);
+
 `ifdef VERILATOR
 
 logic [7:0] debug_value;
-- 
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