From 9777f056d0b37a72276e57d67aa5dbac8b0444b0 Mon Sep 17 00:00:00 2001
From: uvok
Date: Sun, 18 Jan 2026 12:06:46 +0100
Subject: eater: document

---
 eater_cpu/eater_computer.sv | 54 +++++++++++++++++++++++++++++----------------
 1 file changed, 35 insertions(+), 19 deletions(-)

(limited to 'eater_cpu/eater_computer.sv')

diff --git a/eater_cpu/eater_computer.sv b/eater_cpu/eater_computer.sv
index 4985306..41d66b6 100644
--- a/eater_cpu/eater_computer.sv
+++ b/eater_cpu/eater_computer.sv
@@ -3,20 +3,41 @@
 `timescale 1us/1us
 
 module eater_computer(
+  // clock input
   input wire clk_in,
+  // current content of the bus
   output wire [7:0] debug_bus
 );
 
 /* verilator public_on */
-tri [7:0] bus,
+
+// bus: can contain anything - multi driver, thus tri.
+tri [7:0] bus;
+assign debug_bus = bus;
+
+wire [7:0]
+      // Always-output for A (-> ALU)
       A_out,
+      // Always-output for B (-> ALU)
       B_out,
+      // Always-output for RAM
+      // (buffered separately, since I'm re-using code)
       RAM_out,
-      INS_out
+      // Always-output for INStruction register (which is "split" into MSB and LSB)
+      // (buffered separately)
+      INS_out,
+      // Always-output for Memory Address Register.
+      // feeds into RAM, at least the LSB.
+      MAR_out,
+      // PC is only 4 bit, but to output to bus, we want to pad with 0es.
+      PC_out_full
 ;
-tri [3:0] PC_out;
 
-logic A_to_bus, bus_to_A,
+// PC is only 4 bit.
+wire [3:0] PC_in, PC_out;
+
+logic
+      A_to_bus, bus_to_A,
       B_to_bus, bus_to_B,
       INS_to_bus, bus_to_INS,
       RAM_to_bus, bus_to_RAM,
@@ -25,7 +46,6 @@ logic A_to_bus, bus_to_A,
       bus_to_MAR
 ;
 
-assign debug_bus = bus;
 /* verilator public_off */
 
 eater_register A (
@@ -48,20 +68,18 @@ eater_register B (
   // .data(bus)
 );
 
-wire [7:0] INS_out_full;
-
 eater_register INS (
   .clk_in(clk_in),
   .en_store_in(bus_to_INS),
   .en_output_in(INS_to_bus),
   .data_in(bus),
   .bus_out(),
-  .always_out(INS_out_full)
-  // .data(INS_out)
+  .always_out(INS_out)
 );
 
 // 4 LSB go from INS to BUS
-wire [7:0] INS_to_bus_interm = {4'b0, INS_out_full[3:0]};
+wire [7:0] INS_to_bus_interm = {4'b0, INS_out[3:0]};
+// TODO: 4 MSB go to decoder, to be implemented.
 
 zbuffer INS_to_bus_buffer (
     .data_in(INS_to_bus_interm),
@@ -69,21 +87,21 @@ zbuffer INS_to_bus_buffer (
     .data_out(bus)
 );
 
-tri [7:0] MEM_ADR_out;
-tri [3:0] RAM_adr_in = MEM_ADR_out[3:0];
-
 eater_register MEM_ADR (
   .clk_in(clk_in),
   .en_store_in(bus_to_MAR),
   .en_output_in(1'b0),
   .data_in(bus),
   .bus_out(),
-  .always_out(MEM_ADR_out)
+  .always_out(MAR_out)
   // .data(mem_adr_bus_out)
 );
 
-// Eater RAM is "technically" synchronous, but still enables write on clk&w_en.
-// However, "my RAM" *always outputs something*, and that's bad.
+wire [3:0] RAM_adr_in = MAR_out[3:0];
+
+// Eater RAM is "technically" synchronous, but still enables write on clk & w_en.
+// However, "my RAM" *always outputs something*, and that's not expected.
+// buffer separately.
 my_mem #(
   .DATA_WIDTH(8),
   .DATA_DEPTH(16)
@@ -114,10 +132,9 @@ eater_alu alu (
   .bus_out(bus)
 );
 
-tri [3:0] PC_in;
 assign PC_in = bus[3:0];
-
 wire PC_clk_neg = ~clk_in;
+
 counter #(
   .DATA_WIDTH(4)
 ) PC (
@@ -128,7 +145,6 @@ counter #(
   .counter_out(PC_out)
 );
 
-tri[7:0] PC_out_full;
 assign PC_out_full = {4'b0, PC_out};
 
 zbuffer PC_to_bus_buffer (
-- 
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