From 86901bfbbdd54e1262489fbeaa144394f3abb3fd Mon Sep 17 00:00:00 2001
From: uvok
Date: Fri, 16 Jan 2026 14:22:26 +0100
Subject: eater: Add ALU

while doing so,
add always_out port for regs
---
 eater_cpu/bus_writer.sv     |  6 +++++-
 eater_cpu/eater_alu.sv      | 17 +++++++++++++++++
 eater_cpu/eater_computer.sv | 46 ++++++++++++++++++++++++++++-----------------
 eater_cpu/eater_register.v  | 22 ++++++++++++----------
 4 files changed, 63 insertions(+), 28 deletions(-)
 create mode 100644 eater_cpu/eater_alu.sv

(limited to 'eater_cpu')

diff --git a/eater_cpu/bus_writer.sv b/eater_cpu/bus_writer.sv
index 6104301..bbe7a0c 100644
--- a/eater_cpu/bus_writer.sv
+++ b/eater_cpu/bus_writer.sv
@@ -1,3 +1,7 @@
+// Debugging the Ben Eater bus, by manually writing data to it.
+
+`timescale 1us/1us
+
 module bus_writer (
     input [7:0] in_value,
     input in_write_to_output,
@@ -6,4 +10,4 @@ module bus_writer (
 
 assign out_value = in_write_to_output ? in_value : 8'bZ;
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/eater_cpu/eater_alu.sv b/eater_cpu/eater_alu.sv
new file mode 100644
index 0000000..b0fa9ae
--- /dev/null
+++ b/eater_cpu/eater_alu.sv
@@ -0,0 +1,17 @@
+// represents the Ben Eater 8bit computer - ALU
+
+`timescale 1us/1us
+
+module eater_alu (
+    input clk_in,
+    input en_output_in,
+
+    input [7:0] A_in,
+    input [7:0] B_in,
+
+    output [7:0] bus_out
+);
+
+assign bus_out = en_output_in ? 0 : 8'bz;
+    
+endmodule
diff --git a/eater_cpu/eater_computer.sv b/eater_cpu/eater_computer.sv
index cace515..4f1aba2 100644
--- a/eater_cpu/eater_computer.sv
+++ b/eater_cpu/eater_computer.sv
@@ -8,30 +8,33 @@ module eater_computer(
 logic clk_in;
 
 /* verilator public_on */
-tri [7:0] bus;
+tri [7:0] bus, A_out, B_out;
 logic A_to_bus, bus_to_A,
       B_to_bus, bus_to_B,
-      INS_to_bus, bus_to_INS
+      INS_to_bus, bus_to_INS,
+      ALU_to_bus
 ;
 
 assign debug_bus = bus;
 /* verilator public_off */
 
 eater_register A (
-  .clk_i(clk_in),
-  .en_store_i(bus_to_A),
-  .en_output_i(A_to_bus),
-  .data_i(bus),
-  .data_o(bus)
+  .clk_in(clk_in),
+  .en_store_in(bus_to_A),
+  .en_output_in(A_to_bus),
+  .data_in(bus),
+  .bus_out(bus),
+  .always_out(A_out)
   // .data(bus)
 );
 
 eater_register B (
-  .clk_i(clk_in),
-  .en_store_i(bus_to_B),
-  .en_output_i(B_to_bus),
-  .data_i(bus),
-  .data_o(bus)
+  .clk_in(clk_in),
+  .en_store_in(bus_to_B),
+  .en_output_in(B_to_bus),
+  .data_in(bus),
+  .bus_out(bus),
+  .always_out(B_out)
   // .data(bus)
 );
 
@@ -39,14 +42,23 @@ tri [7:0] ins_bus_out;
 assign bus[3:0] = ins_bus_out[3:0];
 
 eater_register INS (
-  .clk_i(clk_in),
-  .en_store_i(bus_to_INS),
-  .en_output_i(INS_to_bus),
-  .data_i(bus),
-  .data_o(ins_bus_out)
+  .clk_in(clk_in),
+  .en_store_in(bus_to_INS),
+  .en_output_in(INS_to_bus),
+  .data_in(bus),
+  .bus_out(ins_bus_out),
+  .always_out()
   // .data(ins_bus_out)
 );
 
+eater_alu alu (
+  .clk_in(clk_in),
+  .en_output_in(ALU_to_bus),
+  .A_in(A_out),
+  .B_in(B_out),
+  .bus_out(bus)
+);
+
 `ifdef VERILATOR
 
 logic [7:0] debug_value;
diff --git a/eater_cpu/eater_register.v b/eater_cpu/eater_register.v
index 17da7bd..52c53a4 100644
--- a/eater_cpu/eater_register.v
+++ b/eater_cpu/eater_register.v
@@ -6,30 +6,32 @@
 module eater_register #(
   parameter DATA_WIDTH = 8
 ) (
-  input clk_i,
+  input clk_in,
 
   // store data on rising clk?
-  input en_store_i,
+  input en_store_in,
   // async - output data to bus
-  input en_output_i,
+  input en_output_in,
 
-  input [(DATA_WIDTH-1) : 0] data_i,
-  output [(DATA_WIDTH-1) : 0] data_o
+  input [(DATA_WIDTH-1) : 0] data_in,
+  output [(DATA_WIDTH-1) : 0] bus_out,
+  output [(DATA_WIDTH-1) : 0] always_out
   // inout [(DATA_WIDTH-1) : 0] data
   
 );
 
 reg [(DATA_WIDTH-1) : 0] r_datastore /* verilator public */;
 
-always @(posedge clk_i) begin
-  if (en_store_i) begin
-    r_datastore <= data_i;
+always @(posedge clk_in) begin
+  if (en_store_in) begin
+    r_datastore <= data_in;
     // r_datastore <= data;
   end
 end
 
-assign data_o = en_output_i ? r_datastore : 8'bz;
-// assign data = en_output_i ? r_datastore : 8'bz;
+assign bus_out = en_output_in ? r_datastore : 8'bz;
+assign always_out = r_datastore;
+// assign data = en_output_in ? r_datastore : 8'bz;
 
 endmodule
 
-- 
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