From 01386fae71a30be8cf7f8add56b8b2aaaccb937c Mon Sep 17 00:00:00 2001
From: uvok
Date: Mon, 29 Dec 2025 13:20:07 +0100
Subject: fifo: try implement r/w logic

---
 fifo.v | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

(limited to 'fifo.v')

diff --git a/fifo.v b/fifo.v
index ebc1eee..43410e1 100644
--- a/fifo.v
+++ b/fifo.v
@@ -1,6 +1,6 @@
 module fifo #(
   parameter DATA_WIDTH = 8,
-  parameter DATA_DEPTH = 1024
+  parameter DATA_DEPTH = 8
 ) (
   input rst_i,
   input clk_i,
@@ -14,30 +14,40 @@ module fifo #(
   output data_valid_o,
 
   input [(DATA_WIDTH-1) : 0] data_i,
-  output [(DATA_WIDTH-1) : 0] data_o
+  output reg [(DATA_WIDTH-1) : 0] data_o
 
 );
 
-reg [$clog2(DATA_DEPTH):0] r_count;
+reg [$clog2(DATA_DEPTH)-1:0] r_count;
+reg [(DATA_WIDTH-1) : 0] r_datastore [(DATA_DEPTH-1) : 0];
+reg [$clog2(DATA_DEPTH)-1:0] r_read_addr;
+reg [$clog2(DATA_DEPTH)-1:0] r_write_addr;
 
 initial begin
   r_count = 0;
+  r_read_addr = 0;
+  r_write_addr = 0;
 end
 
 always @(posedge clk_i or negedge rst_i) begin
   if (!rst_i) begin
     r_count <= 0;
+    r_read_addr <= 0;
+    r_write_addr <= 0;
   end else if (write_i && read_i) begin
     // nothing to do
   end else if (write_i && !full_o) begin
     r_count <= r_count + 1;
+    r_datastore[r_write_addr] <= data_i;
+    r_write_addr <= (r_write_addr < (DATA_DEPTH - 1) ? r_write_addr + 1 : 0);
   end else if (read_i && !empty_o) begin
     r_count <= r_count - 1;
+    data_o <= r_datastore[r_read_addr];
+    r_read_addr <= (r_read_addr < (DATA_DEPTH - 1) ? r_read_addr + 1 : 0);
   end
 end
 
 assign empty_o = r_count == 0;
 assign full_o = r_count >= DATA_DEPTH - 1;
 
-
 endmodule
-- 
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