From 13d94613fb0577ea21895e8def6a6f5480c1a991 Mon Sep 17 00:00:00 2001
From: uvok
Date: Mon, 29 Dec 2025 14:08:02 +0100
Subject: fifo: r/w/address logic

---
 fifo.v | 21 +++++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)

(limited to 'fifo.v')

diff --git a/fifo.v b/fifo.v
index 43410e1..5e7a826 100644
--- a/fifo.v
+++ b/fifo.v
@@ -1,6 +1,6 @@
 module fifo #(
   parameter DATA_WIDTH = 8,
-  parameter DATA_DEPTH = 8
+  parameter DATA_DEPTH = 1024
 ) (
   input rst_i,
   input clk_i,
@@ -11,14 +11,15 @@ module fifo #(
   output empty_o,
   output full_o,
 
-  output data_valid_o,
+  //output data_valid_o,
 
   input [(DATA_WIDTH-1) : 0] data_i,
   output reg [(DATA_WIDTH-1) : 0] data_o
 
 );
 
-reg [$clog2(DATA_DEPTH)-1:0] r_count;
+// need to "count" to number *including* depth
+reg [$clog2(DATA_DEPTH + 1)-1:0] r_count;
 reg [(DATA_WIDTH-1) : 0] r_datastore [(DATA_DEPTH-1) : 0];
 reg [$clog2(DATA_DEPTH)-1:0] r_read_addr;
 reg [$clog2(DATA_DEPTH)-1:0] r_write_addr;
@@ -39,15 +40,23 @@ always @(posedge clk_i or negedge rst_i) begin
   end else if (write_i && !full_o) begin
     r_count <= r_count + 1;
     r_datastore[r_write_addr] <= data_i;
-    r_write_addr <= (r_write_addr < (DATA_DEPTH - 1) ? r_write_addr + 1 : 0);
+    // the_verilator wrongly (???) assumes DATA_DEPTH-1 requires 1 more bit than it does?
+    if ({1'b0, r_write_addr} < (DATA_DEPTH - 1))
+      r_write_addr <= r_write_addr + 1;
+    else
+      r_write_addr <= 0;
   end else if (read_i && !empty_o) begin
     r_count <= r_count - 1;
     data_o <= r_datastore[r_read_addr];
-    r_read_addr <= (r_read_addr < (DATA_DEPTH - 1) ? r_read_addr + 1 : 0);
+    // the_verilator wrongly (???) assumes DATA_DEPTH-1 requires 1 more bit than it does?
+    if ({1'b0, r_read_addr} < (DATA_DEPTH - 1))
+      r_read_addr <= r_read_addr + 1;
+    else
+      r_read_addr <= 0;
   end
 end
 
 assign empty_o = r_count == 0;
-assign full_o = r_count >= DATA_DEPTH - 1;
+assign full_o = r_count == DATA_DEPTH;
 
 endmodule
-- 
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