From 1771756006b8528b3a5a598129ac680a1c095189 Mon Sep 17 00:00:00 2001
From: uvok
Date: Thu, 25 Dec 2025 14:48:17 +0100
Subject: led:  rename vars to make more sense

---
 led.v | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'led.v')

diff --git a/led.v b/led.v
index 2827b87..d8557e8 100644
--- a/led.v
+++ b/led.v
@@ -6,15 +6,15 @@ module led (
     output reg [5:0] led    // 6 LEDS pin
 );
 
-reg myclk;
+reg half_sec_clock;
 
-clkdiv bla(
+clkdiv half_sec_divider(
   .rst_i(rst_i),
   .clk(clk),
-  .o_divclk(myclk)
+  .o_divclk(half_sec_clock)
 );
 
-always @(posedge myclk or negedge rst_i) begin
+always @(posedge half_sec_clock or negedge rst_i) begin
     if (!rst_i)
         led <= 6'b111111;
     else
-- 
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