From 89b32b416d23063f42bef5418aa825893bd33b4b Mon Sep 17 00:00:00 2001
From: uvok
Date: Wed, 24 Dec 2025 17:50:33 +0100
Subject: clkdiv: output must be a register

---
 led.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'led.v')

diff --git a/led.v b/led.v
index e99e5ba..2827b87 100644
--- a/led.v
+++ b/led.v
@@ -6,7 +6,7 @@ module led (
     output reg [5:0] led    // 6 LEDS pin
 );
 
-wire myclk;
+reg myclk;
 
 clkdiv bla(
   .rst_i(rst_i),
@@ -16,7 +16,7 @@ clkdiv bla(
 
 always @(posedge myclk or negedge rst_i) begin
     if (!rst_i)
-        led <= 6'b011110;
+        led <= 6'b111111;
     else
 //    else if (counter == 24'd1349_9999)       // 0.5s delay
         led[5:0] <= led[5:0] - 1;
-- 
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