From a5115147fbe0661ca78702e97b0fa3d5277ac83c Mon Sep 17 00:00:00 2001
From: uvok
Date: Wed, 24 Dec 2025 15:57:40 +0100
Subject: Make clock divider separate module

---
 led.v | 29 +++++++++++++++--------------
 1 file changed, 15 insertions(+), 14 deletions(-)

(limited to 'led.v')

diff --git a/led.v b/led.v
index 772415f..e99e5ba 100644
--- a/led.v
+++ b/led.v
@@ -1,28 +1,29 @@
+`include "clkdiv.v"
+
 module led (
     input clk,              // clk input
     input rst_i,              // reset input
     output reg [5:0] led    // 6 LEDS pin
 );
 
-reg [23:0] counter;
+wire myclk;
 
-always @(posedge clk or negedge rst_i) begin
-    if (!rst_i)
-        counter <= 24'd0;
-    else if (counter < 24'd1349_9999)       // 0.5s delay
-        counter <= counter + 1'b1;
-    else
-        counter <= 24'd0;
-end
+clkdiv bla(
+  .rst_i(rst_i),
+  .clk(clk),
+  .o_divclk(myclk)
+);
 
-always @(posedge clk or negedge rst_i) begin
+always @(posedge myclk or negedge rst_i) begin
     if (!rst_i)
-        led <= 6'b111110;
-    else if (counter == 24'd1349_9999)       // 0.5s delay
-        led[5:0] <= led[5:0] - 1;
+        led <= 6'b011110;
     else
-        led <= led;
+//    else if (counter == 24'd1349_9999)       // 0.5s delay
+        led[5:0] <= led[5:0] - 1;
+//    else
+//        led <= led;
 end
 
+
 endmodule
 
-- 
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