From e0970b34d629eb765e6e488f6c43caef1620faf3 Mon Sep 17 00:00:00 2001
From: uvok
Date: Tue, 23 Dec 2025 19:37:13 +0100
Subject: Add FPGA basics

---
 led.v | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 led.v

(limited to 'led.v')

diff --git a/led.v b/led.v
new file mode 100644
index 0000000..772415f
--- /dev/null
+++ b/led.v
@@ -0,0 +1,28 @@
+module led (
+    input clk,              // clk input
+    input rst_i,              // reset input
+    output reg [5:0] led    // 6 LEDS pin
+);
+
+reg [23:0] counter;
+
+always @(posedge clk or negedge rst_i) begin
+    if (!rst_i)
+        counter <= 24'd0;
+    else if (counter < 24'd1349_9999)       // 0.5s delay
+        counter <= counter + 1'b1;
+    else
+        counter <= 24'd0;
+end
+
+always @(posedge clk or negedge rst_i) begin
+    if (!rst_i)
+        led <= 6'b111110;
+    else if (counter == 24'd1349_9999)       // 0.5s delay
+        led[5:0] <= led[5:0] - 1;
+    else
+        led <= led;
+end
+
+endmodule
+
-- 
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