From 9ea9ee4c219fd7e1687275870cb2aecbd731c7dd Mon Sep 17 00:00:00 2001
From: uvok
Date: Tue, 30 Dec 2025 09:33:21 +0100
Subject: my_mem: Use nededge for timing

---
 my_mem.tb.v | 32 ++++++++++----------------------
 1 file changed, 10 insertions(+), 22 deletions(-)

(limited to 'my_mem.tb.v')

diff --git a/my_mem.tb.v b/my_mem.tb.v
index 63eaba4..c8c2e12 100644
--- a/my_mem.tb.v
+++ b/my_mem.tb.v
@@ -53,58 +53,46 @@ module my_mem_tb();
     r_write_addr = '0;
     data_i = '0;
 
-    repeat (3) @(posedge clk);
+    repeat (3) @(negedge clk);
 
     // -------------------------
     // Write some values
     // -------------------------
-    @(posedge clk);
-    #1
+    @(negedge clk);
     write_en_i   = 1;
     r_write_addr = 10;
     data_i       = 8'hA5;
 
-    @(posedge clk);
-    #1
+    @(negedge clk);
     r_write_addr = 11;
     data_i       = 8'h3C;
 
-    @(posedge clk);
-    #1
+    @(negedge clk);
     write_en_i = 0;
 
     // -------------------------
     // Read back values
     // -------------------------
 
-    // asserts fail in iverilog if I use the posedge stuff,
-    // (but works in verilator).
-    // need an additional clock cycle delay.
-
-    @(posedge clk);
-    #1
+    @(negedge clk);
     read_en_i   = 1;
     r_read_addr = 10;
 
-    @(posedge clk);
-    #1
+    @(negedge clk);
     assert (data_o == 8'hA5)
     else $error("ASSERTION FAILED: addr 10 expected 0xA5, got 0x%02h", data_o);
 
-    @(posedge clk);
-    #1
+    @(negedge clk);
     r_read_addr = 11;
 
-    @(posedge clk);
-    #1
+    @(negedge clk);
     assert (data_o == 8'h3C)
     else $error("ASSERTION FAILED: addr 11 expected 0x3C, got 0x%02h", data_o);
 
-    @(posedge clk);
-    #1
+    @(negedge clk);
     read_en_i = 0;
 
-    repeat (3) @(posedge clk);
+    repeat (3) @(negedge clk);
     $finish;
   end
 
-- 
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