From 47c26f27b8be4c6c22ed81f701f1b25072bb3341 Mon Sep 17 00:00:00 2001
From: uvok
Date: Fri, 16 Jan 2026 18:22:10 +0100
Subject: (System)Verilog: Be explicit about wire/logic

---
 nandgame/alu.sv | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'nandgame/alu.sv')

diff --git a/nandgame/alu.sv b/nandgame/alu.sv
index 54297c9..5f82a64 100644
--- a/nandgame/alu.sv
+++ b/nandgame/alu.sv
@@ -13,17 +13,17 @@ module  alu #(
   parameter DATA_WIDTH = 16
 ) (
   // "X" operand
-  input [(DATA_WIDTH-1):0] X_in,
+  input wire [(DATA_WIDTH-1):0] X_in,
   // "Y" operand
-  input [(DATA_WIDTH-1):0] Y_in,
+  input wire [(DATA_WIDTH-1):0] Y_in,
   // "u" flag. 1=arithmetic, 0=logic operation
-  input logic u_arith_nlogic_in,
+  input wire u_arith_nlogic_in,
   // opcode, see ArithCode / LogicCode
-  input logic [1:0] opcode_in,
+  input wire [1:0] opcode_in,
   // zero the "X" operand
-  input logic zx_in,
+  input wire zx_in,
   // swap "X" and "Y" operands
-  input logic sw_in,
+  input wire sw_in,
 
   // result of operation
   output logic [(DATA_WIDTH-1):0] result_out
-- 
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