From 6c1db8cded8b8bb1c4d31a840f7dd9dddb8bbf7d Mon Sep 17 00:00:00 2001
From: uvok
Date: Fri, 2 Jan 2026 19:36:30 +0100
Subject: Rename variables to be more clear, document

---
 nandgame/alu.sv | 55 +++++++++++++++++++++++++++++++------------------------
 1 file changed, 31 insertions(+), 24 deletions(-)

(limited to 'nandgame/alu.sv')

diff --git a/nandgame/alu.sv b/nandgame/alu.sv
index 6aef925..f452d32 100644
--- a/nandgame/alu.sv
+++ b/nandgame/alu.sv
@@ -12,41 +12,48 @@
 module  alu #(
   parameter DATA_WIDTH = 16
 ) (
-  input [(DATA_WIDTH-1):0] X,
-  input [(DATA_WIDTH-1):0] Y,
-  input logic u,
-  input logic [1:0] opcode,
-  input logic zx,
-  input logic sw,
-
-  output logic [(DATA_WIDTH-1):0] RES
+  // "X" operand
+  input [(DATA_WIDTH-1):0] X_in,
+  // "Y" operand
+  input [(DATA_WIDTH-1):0] Y_in,
+  // "u" flag. 1=arithmetic, 0=logic operation
+  input logic u_arith_nlogic_in,
+  // opcode, see ArithCode / LogicCode
+  input logic [1:0] opcode_in,
+  // zero the "X" operand
+  input logic zx_in,
+  // swap "X" and "Y" operands
+  input logic sw_in,
+
+  // result of operation
+  output logic [(DATA_WIDTH-1):0] result_out
 );
 
-logic [(DATA_WIDTH-1):0] MyX;
+logic [(DATA_WIDTH-1):0] int_op_x;
+logic [(DATA_WIDTH-1):0] int_op_y;
 
-logic [(DATA_WIDTH-1):0] MyY;
-logic [(DATA_WIDTH-1):0] MyResA;
-logic [(DATA_WIDTH-1):0] MyResL;
+logic [(DATA_WIDTH-1):0] int_result_arith;
+logic [(DATA_WIDTH-1):0] int_result_logic;
 
-assign MyX = zx ? 0 : sw ? Y : X;
-assign MyY = sw ? X : Y;
+assign int_op_x = zx_in ? 0
+                  : (sw_in ? Y_in : X_in);
+assign int_op_y = sw_in ? X_in : Y_in;
 
 arith_unit au (
-  .X(MyX),
-  .Y(MyY),
-  .RES(MyResA),
-  .operation(opcode)
+  .X_in(int_op_x),
+  .Y_in(int_op_y),
+  .result_out(int_result_arith),
+  .arith_operation_in(ArithCode'(opcode_in))
 );
 
 logic_unit lu (
-  .X(MyX),
-  .Y(MyY),
-  .RES(MyResL),
-  .operation(opcode)
+  .X_in(int_op_x),
+  .Y_in(int_op_y),
+  .result_out(int_result_logic),
+  .logic_operation_in(LogicCode'(opcode_in))
 );
 
-assign RES = u ? MyResA : MyResL;
-
+assign result_out = u_arith_nlogic_in ? int_result_arith : int_result_logic;
 
 endmodule
 
-- 
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