From 47c26f27b8be4c6c22ed81f701f1b25072bb3341 Mon Sep 17 00:00:00 2001
From: uvok
Date: Fri, 16 Jan 2026 18:22:10 +0100
Subject: (System)Verilog: Be explicit about wire/logic

---
 nandgame/arith_unit.sv | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'nandgame/arith_unit.sv')

diff --git a/nandgame/arith_unit.sv b/nandgame/arith_unit.sv
index 53ea17e..75736ab 100644
--- a/nandgame/arith_unit.sv
+++ b/nandgame/arith_unit.sv
@@ -11,11 +11,11 @@ module  arith_unit #(
   parameter DATA_WIDTH = 16
 ) (
   // first operand
-  input [(DATA_WIDTH-1):0] X_in,
+  input wire [(DATA_WIDTH-1):0] X_in,
   // second operand
-  input [(DATA_WIDTH-1):0] Y_in,
+  input wire [(DATA_WIDTH-1):0] Y_in,
   // opcode, see ArithCode
-  input ArithCode arith_operation_in,
+  input wire ArithCode arith_operation_in,
 
   // result of operation
   output logic [(DATA_WIDTH-1):0] result_out
-- 
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