From 47c26f27b8be4c6c22ed81f701f1b25072bb3341 Mon Sep 17 00:00:00 2001
From: uvok
Date: Fri, 16 Jan 2026 18:22:10 +0100
Subject: (System)Verilog: Be explicit about wire/logic

---
 nandgame/computer.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'nandgame/computer.sv')

diff --git a/nandgame/computer.sv b/nandgame/computer.sv
index 5c2127f..3286bfe 100644
--- a/nandgame/computer.sv
+++ b/nandgame/computer.sv
@@ -8,8 +8,8 @@
 `include "counter.sv"
 
 module computer (
-  input clk_in,
-  output halt
+  input wire clk_in,
+  output wire halt
 );
 
 wire nclk_int;
-- 
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