From 47c26f27b8be4c6c22ed81f701f1b25072bb3341 Mon Sep 17 00:00:00 2001
From: uvok
Date: Fri, 16 Jan 2026 18:22:10 +0100
Subject: (System)Verilog: Be explicit about wire/logic

---
 nandgame/cond_check.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'nandgame/cond_check.sv')

diff --git a/nandgame/cond_check.sv b/nandgame/cond_check.sv
index 3961313..6aa8289 100644
--- a/nandgame/cond_check.sv
+++ b/nandgame/cond_check.sv
@@ -9,7 +9,7 @@ module  cond_check #(
   parameter DATA_WIDTH = 16
 ) (
   // operand
-  input [(DATA_WIDTH-1):0] X_in,
+  input wire [(DATA_WIDTH-1):0] X_in,
   // check whether operand < 0
   input wire check_ltz_in,
   // check whether operand == 0
-- 
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