From 6c1db8cded8b8bb1c4d31a840f7dd9dddb8bbf7d Mon Sep 17 00:00:00 2001
From: uvok
Date: Fri, 2 Jan 2026 19:36:30 +0100
Subject: Rename variables to be more clear, document

---
 nandgame/cond_check.sv | 30 +++++++++++++++++++-----------
 1 file changed, 19 insertions(+), 11 deletions(-)

(limited to 'nandgame/cond_check.sv')

diff --git a/nandgame/cond_check.sv b/nandgame/cond_check.sv
index d5344ba..3961313 100644
--- a/nandgame/cond_check.sv
+++ b/nandgame/cond_check.sv
@@ -8,20 +8,28 @@
 module  cond_check #(
   parameter DATA_WIDTH = 16
 ) (
-  input [(DATA_WIDTH-1):0] X,
-  input wire ltz,
-  input wire eqz,
-  input wire gtz,
-  output wire res
+  // operand
+  input [(DATA_WIDTH-1):0] X_in,
+  // check whether operand < 0
+  input wire check_ltz_in,
+  // check whether operand == 0
+  input wire check_eqz_in,
+  // check whether operand > 0
+  input wire check_gtz_in,
+
+  // result of check
+  output wire result_out
 );
 
-wire ltr, eqr, gtr, greater_zero;
-assign greater_zero = X[(DATA_WIDTH - 1)] == 0;
-assign ltr = ltz && !greater_zero;
-assign gtr = gtz && greater_zero && !(X == 0);
-assign eqr = eqz && (X == 0);
+wire is_neg_int;
+assign is_neg_int = X_in[(DATA_WIDTH - 1)] == 1;
+
+wire ltz_result_int, eqz_result_int, gtz_result_int;
+assign ltz_result_int = check_ltz_in && is_neg_int;
+assign gtz_result_int = check_gtz_in && !is_neg_int && !(X_in == 0);
+assign eqz_result_int = check_eqz_in && (X_in == 0);
 
-assign res = ltr || gtr || eqr;
+assign result_out = ltz_result_int || gtz_result_int || eqz_result_int;
 
 endmodule
 
-- 
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