From 47c26f27b8be4c6c22ed81f701f1b25072bb3341 Mon Sep 17 00:00:00 2001
From: uvok
Date: Fri, 16 Jan 2026 18:22:10 +0100
Subject: (System)Verilog: Be explicit about wire/logic

---
 nandgame/counter.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'nandgame/counter.sv')

diff --git a/nandgame/counter.sv b/nandgame/counter.sv
index 90afa9b..2089194 100644
--- a/nandgame/counter.sv
+++ b/nandgame/counter.sv
@@ -9,7 +9,7 @@ module  counter #(
   parameter DATA_WIDTH = 16
 ) (
   // input / value to store in counter
-  input [(DATA_WIDTH-1):0] X_in,
+  input wire [(DATA_WIDTH-1):0] X_in,
   // whether to store input (else increment)
   input wire st_store_X_in,
   // clock
-- 
cgit v1.2.3