From 6c1db8cded8b8bb1c4d31a840f7dd9dddb8bbf7d Mon Sep 17 00:00:00 2001
From: uvok
Date: Fri, 2 Jan 2026 19:36:30 +0100
Subject: Rename variables to be more clear, document

---
 nandgame/counter.sv | 43 ++++++++++++++++++++++---------------------
 1 file changed, 22 insertions(+), 21 deletions(-)

(limited to 'nandgame/counter.sv')

diff --git a/nandgame/counter.sv b/nandgame/counter.sv
index 78f054e..988d123 100644
--- a/nandgame/counter.sv
+++ b/nandgame/counter.sv
@@ -5,46 +5,47 @@
 module  counter #(
   parameter DATA_WIDTH = 16
 ) (
-  input [(DATA_WIDTH-1):0] X,
-  input wire st,
-  // probably opposed to nandgame,
-  // which "stores" on rising clock
-  // and "outputs" on falling clock,
-  // use "regular" stuff??? 
-  input wire cl,
-  output wire [(DATA_WIDTH-1):0] count
+  // input / value to store in counter
+  input [(DATA_WIDTH-1):0] X_in,
+  // whether to store input (else increment)
+  input wire st_store_X_in,
+  // clock
+  input wire clk_in,
+
+  // counter value
+  output wire [(DATA_WIDTH-1):0] counter_out
 );
 
 
 /*
 A counter component increments a 16-bit number for each clock cycle.
 
-If st (store) is 1, then the input value X is used as the new counter value.
+If st_store_X_in (store) is 1, then the input value X_in is used as the new counter value.
 
-If st is 0, then the previous counter value is incremented by 1.
+If st_store_X_in is 0, then the previous counter value is incremented by 1.
 
-The counter output changes when cl (clock signal) changes to 0.
+The counter output changes when clk_in (clock signal) changes to 0.
 Input	Effect
-st	cl	
+st_store_X_in	clk_in	
 0	0	set next to output + 1
-1	0	set next to X
+1	0	set next to X_in
 
-output is the current output of the component. next becomes the current output when cl changes to 0.
+output is the current output of the component. next becomes the current output when clk_in changes to 0.
 */
 
-reg [(DATA_WIDTH-1):0] r_ctr;
+reg [(DATA_WIDTH-1):0] counter_int;
 
 initial begin
-  r_ctr = 0;
+  counter_int = 0;
 end
 
-always @(negedge cl) begin
-  if (st)
-    r_ctr <= X;
+always @(negedge clk_in) begin
+  if (st_store_X_in)
+    counter_int <= X_in;
   else
-    r_ctr <= r_ctr + 1;
+    counter_int <= counter_int + 1;
 end
 
-assign count = r_ctr;
+assign counter_out = counter_int;
 
 endmodule
-- 
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