From 762e2526249a9829b58fc8492d4db9ebd6e82589 Mon Sep 17 00:00:00 2001
From: uvok
Date: Thu, 1 Jan 2026 17:03:55 +0100
Subject: Add counter

---
 nandgame/counter.sv | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 nandgame/counter.sv

(limited to 'nandgame/counter.sv')

diff --git a/nandgame/counter.sv b/nandgame/counter.sv
new file mode 100644
index 0000000..8fa1d2b
--- /dev/null
+++ b/nandgame/counter.sv
@@ -0,0 +1,35 @@
+// nandgame counter
+
+`timescale 1us/1us
+
+module  counter #(
+  parameter DATA_WIDTH = 16
+) (
+  input [(DATA_WIDTH-1):0] X,
+  input wire st,
+  // probably opposed to nandgame,
+  // which "stores" on rising clock
+  // and "outputs" on falling clock,
+  // use "regular" stuff??? 
+  input wire cl,
+  output reg [(DATA_WIDTH-1):0] RES
+);
+
+
+/*
+A counter component increments a 16-bit number for each clock cycle.
+
+If st (store) is 1, then the input value X is used as the new counter value.
+
+If st is 0, then the previous counter value is incremented by 1.
+
+The counter output changes when cl (clock signal) changes to 0.
+Input	Effect
+st	cl	
+0	0	set next to output + 1
+1	0	set next to X
+
+output is the current output of the component. next becomes the current output when cl changes to 0.
+*/
+
+endmodule
-- 
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