From e259ea68ac0bc07c231e9f2a44b98a1ad42adb73 Mon Sep 17 00:00:00 2001
From: uvok
Date: Fri, 26 Dec 2025 20:00:13 +0100
Subject: p2s: Rename input, improve latency

start clock out data right away.
---
 par_to_ser.tb.v | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)

(limited to 'par_to_ser.tb.v')

diff --git a/par_to_ser.tb.v b/par_to_ser.tb.v
index bc87f6f..2d1fc6d 100644
--- a/par_to_ser.tb.v
+++ b/par_to_ser.tb.v
@@ -5,14 +5,14 @@ module par_to_ser_tb (
 
 reg clk_i;
 reg rst_i;
-reg do_send_i;
+reg data_valid_i;
 reg [7:0] dat_i;
 wire dat_o;
 
 par_to_ser uut(
   .clk_i(clk_i),
   .rst_i(rst_i),
-  .do_send_i(do_send_i),
+  .data_valid_i(data_valid_i),
   .dat_i(dat_i),
   .dat_o(dat_o)
 );
@@ -21,7 +21,7 @@ initial begin
   $dumpfile("par_to_ser.lxt2"); $dumpvars();
   clk_i <= 0;
   rst_i <= 1'b1;
-  do_send_i <= 1'b0;
+  data_valid_i <= 1'b0;
 
   #1
   rst_i <= 1'b0;
@@ -33,13 +33,17 @@ always #10 clk_i = ~clk_i;
 
 initial begin
   #37
-  dat_i <= 8'haa;
+  dat_i <= 8'b00110011;
   #13
-  do_send_i <= 1'b1;
+  data_valid_i <= 1'b1;
+
+  // clock data in
+  #20
+
   // wait 8 clock cycles?
-  #80
+  #160
 
-  do_send_i <= 1'b0;
+  data_valid_i <= 1'b0;
 
   #400
   $finish();
-- 
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