From 4134cbac5dd1c87aa17a1eda68f69d5707529390 Mon Sep 17 00:00:00 2001
From: uvok
Date: Sat, 27 Dec 2025 11:38:52 +0100
Subject: p2s: rewrite logic

split blocks.
Better separate counting/sending logic.
---
 par_to_ser.v | 32 +++++++++++++-------------------
 1 file changed, 13 insertions(+), 19 deletions(-)

(limited to 'par_to_ser.v')

diff --git a/par_to_ser.v b/par_to_ser.v
index c4fb13b..d4e4254 100644
--- a/par_to_ser.v
+++ b/par_to_ser.v
@@ -9,31 +9,28 @@ module par_to_ser #(
   input [(SHIFT_WIDTH-1):0] dat_i,
   output reg dat_o
 );
-//parameter SHIFT_WIDTH = 8;
 
-// reg sending = 1'b0;
+// Learning: can't declate parameter here
+// if I want to use it in the input/output list.
+// parameter SHIFT_WIDTH = 8;
+
 reg [7:0] send_data = 8'hff;
 // want to count to number *including* width, add 1
 reg [$clog2(SHIFT_WIDTH + 1) - 1:0] count = 0;
-reg sending = 1'b0;
 
-always @(posedge clk_i or negedge rst_i) begin
-  if (!rst_i) begin
-    sending <= 1'b0;
-  end else if (data_valid_i && count == 0) begin
-    sending <= 1;
-  end else if (count == SHIFT_WIDTH) begin
-    sending <= 0;
-  end
-end
+wire counting, sending;
+
+// sending is one byte longer
+assign sending = (count != 0) && (count <= SHIFT_WIDTH);
+// yes, smaller than, the count *to* 8 still takes place
+assign counting = (count != 0) && (count < SHIFT_WIDTH);
 
 always @(posedge clk_i or negedge rst_i) begin
   if (!rst_i) begin
     dat_o <= 1'b1;
   end else if (data_valid_i && count == 0) begin
     dat_o <= dat_i[0];
-  end
-  else if (sending) begin
+  end else if (sending) begin
     dat_o <= send_data[0];
   end
 end
@@ -43,8 +40,7 @@ always @(posedge clk_i or negedge rst_i) begin
     send_data <= 8'hff;
   end else if (data_valid_i && count == 0) begin
     send_data <= {1'b1, dat_i[7:1]};
-  end
-  else if (sending) begin
+  end else if (sending) begin
     // arbitrary decision: register is filled with a 1
     send_data <= {1'b1, send_data[7:1]};
   end
@@ -55,9 +51,7 @@ always @(posedge clk_i or negedge rst_i) begin
     count <= 0;
   end else if (data_valid_i && count == 0) begin
     count <= 1;
-  end
-  // yes, smaller, the count *to* 8 still takes place
-  else if (sending && count < SHIFT_WIDTH) begin
+  end else if (counting) begin
     count <= count + 1;
   end else begin
     count <= 0;
-- 
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